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Searched refs:MC_SEQ_MISC_TIMING2_LP (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dbtcd.h150 #define MC_SEQ_MISC_TIMING2_LP 0x2a78 macro
H A Dbtc_dpm.c1867 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; in btc_check_s0_mc_reg_index()
2030 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); in btc_initialize_mc_reg_table()
H A Dnid.h808 #define MC_SEQ_MISC_TIMING2_LP 0x2a78 macro
H A Dsid.h576 #define MC_SEQ_MISC_TIMING2_LP 0x2a78 macro
H A Dcikd.h701 #define MC_SEQ_MISC_TIMING2_LP 0x2a78 macro
H A Devergreend.h326 #define MC_SEQ_MISC_TIMING2_LP 0x2a78 macro
H A Dni_dpm.c2781 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; in ni_check_s0_mc_reg_index()
2884 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); in ni_initialize_mc_reg_table()
H A Dcypress_dpm.c983 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2; in cypress_set_mc_reg_address_table()
H A Dci_dpm.c4465 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; in ci_check_s0_mc_reg_index()
4676 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); in ci_initialize_mc_reg_table()
H A Dsi_dpm.c5439 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; in si_check_s0_mc_reg_index()
5546 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); in si_initialize_mc_reg_table()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsi_dpm.c5894 *out_reg = MC_SEQ_MISC_TIMING2_LP; in si_check_s0_mc_reg_index()
6001 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); in si_initialize_mc_reg_table()