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Searched refs:MC_SEQ_RD_CTL_D1 (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dbtcd.h110 #define MC_SEQ_RD_CTL_D1 0x28b8 macro
H A Dbtc_dpm.c1872 case MC_SEQ_RD_CTL_D1 >> 2: in btc_check_s0_mc_reg_index()
2032 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); in btc_initialize_mc_reg_table()
H A Dnid.h786 #define MC_SEQ_RD_CTL_D1 0x28b8 macro
H A Dsid.h547 #define MC_SEQ_RD_CTL_D1 0x28b8 macro
H A Dcikd.h660 #define MC_SEQ_RD_CTL_D1 0x28b8 macro
H A Devergreend.h292 #define MC_SEQ_RD_CTL_D1 0x28b8 macro
H A Dni_dpm.c2786 case MC_SEQ_RD_CTL_D1 >> 2: in ni_check_s0_mc_reg_index()
2891 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); in ni_initialize_mc_reg_table()
H A Dcypress_dpm.c992 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2; in cypress_set_mc_reg_address_table()
H A Dci_dpm.c4476 case MC_SEQ_RD_CTL_D1 >> 2: in ci_check_s0_mc_reg_index()
4683 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); in ci_initialize_mc_reg_table()
H A Dsi_dpm.c5444 case MC_SEQ_RD_CTL_D1 >> 2: in si_check_s0_mc_reg_index()
5553 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); in si_initialize_mc_reg_table()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsi_dpm.c5899 case MC_SEQ_RD_CTL_D1: in si_check_s0_mc_reg_index()
6008 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); in si_initialize_mc_reg_table()