Home
last modified time | relevance | path

Searched refs:MC_SEQ_WR_CTL_D0_LP (Results 1 – 11 of 11) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dbtcd.h151 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c macro
H A Dbtc_dpm.c1876 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; in btc_check_s0_mc_reg_index()
2033 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in btc_initialize_mc_reg_table()
H A Dnid.h809 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c macro
H A Dsid.h577 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c macro
H A Dcikd.h702 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c macro
H A Devergreend.h327 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c macro
H A Dni_dpm.c2790 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; in ni_check_s0_mc_reg_index()
2888 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in ni_initialize_mc_reg_table()
H A Dcypress_dpm.c995 eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2; in cypress_set_mc_reg_address_table()
H A Dci_dpm.c4480 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; in ci_check_s0_mc_reg_index()
4680 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in ci_initialize_mc_reg_table()
H A Dsi_dpm.c5448 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; in si_check_s0_mc_reg_index()
5550 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in si_initialize_mc_reg_table()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsi_dpm.c5903 *out_reg = MC_SEQ_WR_CTL_D0_LP; in si_check_s0_mc_reg_index()
6005 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); in si_initialize_mc_reg_table()