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Searched refs:NUM_BANKS (Results 1 – 12 of 12) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dgfx_v8_0.c2350 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2354 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2358 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2362 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2366 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2370 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2374 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2542 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2546 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2550 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
[all …]
H A Dcikd.h199 # define NUM_BANKS(x) ((x) << 6) macro
H A Ddce_v10_0.c1958 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v10_0_crtc_do_set_base()
H A Ddce_v11_0.c2000 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in dce_v11_0_crtc_do_set_base()
H A Dgfx_v9_0.c1236 NUM_BANKS); in gfx_v9_0_gpu_early_init()
/dragonfly/sys/dev/drm/radeon/
H A Dsi.c2510 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2519 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2528 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2537 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2546 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2555 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2564 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2573 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2582 NUM_BANKS(ADDR_SURF_16_BANK) | in si_tiling_mode_table_init()
2708 NUM_BANKS(ADDR_SURF_8_BANK) | in si_tiling_mode_table_init()
[all …]
H A Dcik.c2626 NUM_BANKS(ADDR_SURF_8_BANK)); in cik_tiling_mode_table_init()
2630 NUM_BANKS(ADDR_SURF_4_BANK)); in cik_tiling_mode_table_init()
2634 NUM_BANKS(ADDR_SURF_2_BANK)); in cik_tiling_mode_table_init()
2654 NUM_BANKS(ADDR_SURF_8_BANK)); in cik_tiling_mode_table_init()
2658 NUM_BANKS(ADDR_SURF_4_BANK)); in cik_tiling_mode_table_init()
2662 NUM_BANKS(ADDR_SURF_2_BANK)); in cik_tiling_mode_table_init()
2855 NUM_BANKS(ADDR_SURF_8_BANK)); in cik_tiling_mode_table_init()
2859 NUM_BANKS(ADDR_SURF_4_BANK)); in cik_tiling_mode_table_init()
2883 NUM_BANKS(ADDR_SURF_8_BANK)); in cik_tiling_mode_table_init()
2887 NUM_BANKS(ADDR_SURF_4_BANK)); in cik_tiling_mode_table_init()
[all …]
H A Dsid.h1221 # define NUM_BANKS(x) ((x) << 20) macro
H A Dcikd.h1275 # define NUM_BANKS(x) ((x) << 6) macro
/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_hubp.h258 HUBP_SF(HUBP0_DCSURF_ADDR_CONFIG, NUM_BANKS, mask_sh),\
437 type NUM_BANKS;\
H A Ddcn10_hubp.c142 NUM_BANKS, log_2(info->gfx9.num_banks), in hubp1_program_tiling()
/dragonfly/sys/dev/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c2089 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); in fill_plane_attributes_from_fb()