| /dragonfly/sys/dev/netif/ath/ath_hal/ar9002/ |
| H A D | ar9285_btcoex.c | 72 OS_REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000); in ar9285BTCoexAntennaDiversity()
88 OS_REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0x60000000, 0xf0000000); in ar9285BTCoexAntennaDiversity()
103 OS_REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000); in ar9285BTCoexAntennaDiversity()
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| H A D | ar9285_reset.c | 371 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr); in ar9285SetBoardValues()
372 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr); in ar9285SetBoardValues()
373 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr); in ar9285SetBoardValues()
378 OS_REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr); in ar9285SetBoardValues()
383 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr); in ar9285SetBoardValues()
384 OS_REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr); in ar9285SetBoardValues()
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| /dragonfly/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_gpio.c | 103 OS_REG_RMW(ah, addr, (type << gpio_shift), (0x1f << gpio_shift)); in ar9300_gpio_cfg_output_mux()
229 OS_REG_RMW(ah, in ar9300_gpio_cfg_output()
330 OS_REG_RMW(ah, in ar9300_gpio_cfg_output_led_off()
361 OS_REG_RMW(ah, in ar9300_gpio_cfg_input()
381 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT), in ar9300_gpio_set()
401 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN), in ar9300_gpio_get()
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| H A D | ar9300_reset.c | 169 OS_REG_RMW(ah, in ar9300_init_mfp()
187 OS_REG_RMW(ah, in ar9300_init_mfp()
1982 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1), 0x0, 0x1f); in ar9300_phy_disable()
3012 OS_REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | in ar9300_process_ini()
3016 OS_REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | in ar9300_process_ini()
3018 OS_REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | in ar9300_process_ini()
3043 OS_REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | in ar9300_process_ini()
3045 OS_REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | in ar9300_process_ini()
3047 OS_REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S | in ar9300_process_ini()
5201 OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB | AR_CFG_SWRB, 0); in ar9300_reset()
[all …]
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| H A D | ar9300.h | 1184 #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB | AR_CFG_SWRB,0)
1186 #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB,0)
1189 #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWRB,0)
1191 #define ar9300_init_cfg_reg(ah) OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD,0)
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| H A D | ar9300_eeprom.c | 2280 OS_REG_RMW(ah, AR_PHY_TPC_11_B0, in ar9300_power_control_override()
2284 OS_REG_RMW(ah, AR_PHY_TPC_11_B1, in ar9300_power_control_override()
2288 OS_REG_RMW(ah, AR_PHY_TPC_11_B2, in ar9300_power_control_override()
2296 OS_REG_RMW(ah, AR_PHY_TPC_6_B0, in ar9300_power_control_override()
2299 OS_REG_RMW(ah, AR_PHY_TPC_6_B1, in ar9300_power_control_override()
2302 OS_REG_RMW(ah, AR_PHY_TPC_6_B2, in ar9300_power_control_override()
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| H A D | ar9300_misc.c | 2620 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU), in ar9300_bt_coex_enable()
3048 OS_REG_RMW(ah, AR_PHY_TPC_11_B0, in ar9300_chk_rssi_update_tx_pwr()
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| /dragonfly/sys/dev/netif/ath/ath_hal/ar5416/ |
| H A D | ar5416_gpio.c | 69 OS_REG_RMW(ah, addr, (type << gpio_shift), in cfgOutputMux()
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| H A D | ar5416_btcoex.c | 317 OS_REG_RMW(ah, AR_GPIO_PDPU, in ar5416BTCoexEnable()
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| /dragonfly/sys/dev/netif/ath/ath_hal/ |
| H A D | ah_internal.h | 581 #define OS_REG_RMW(_a, _r, _set, _clr) \ macro
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