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Searched refs:PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h8167 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000L macro
H A Ddce_8_0_sh_mask.h35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000 macro
H A Ddce_10_0_sh_mask.h35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000 macro
H A Ddce_11_0_sh_mask.h35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000 macro
H A Ddce_11_2_sh_mask.h35 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK 0x10000000 macro
H A Ddce_12_0_sh_mask.h3303 #define PIPE0_PG_STATUS__PIPE0_DESIRED_PWR_STATE_MASK … macro