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Searched refs:PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h8230 #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x0000001e macro
H A Ddce_8_0_sh_mask.h82 #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e macro
H A Ddce_10_0_sh_mask.h82 #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e macro
H A Ddce_11_2_sh_mask.h82 #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT 0x1e macro
H A Ddce_12_0_sh_mask.h3335 #define PIPE3_PG_STATUS__PIPE3_PGFSM_PWR_STATUS__SHIFT … macro