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Searched refs:PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK (Results 1 – 5 of 5) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h8269 #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000L macro
H A Ddce_8_0_sh_mask.h109 #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000 macro
H A Ddce_10_0_sh_mask.h109 #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000 macro
H A Ddce_11_2_sh_mask.h109 #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK 0xc0000000 macro
H A Ddce_12_0_sh_mask.h3359 #define PIPE5_PG_STATUS__PIPE5_PGFSM_PWR_STATUS_MASK … macro