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Searched refs:PPSMC_MSG_MCLKDPM_SetEnabledMask (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dppsmc.h131 #define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) macro
H A Dci_dpm.c1752 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n); in ci_dpm_force_state_mclk()
3869 PPSMC_MSG_MCLKDPM_SetEnabledMask, in ci_upload_dpm_level_enable_mask()
3993 PPSMC_MSG_MCLKDPM_SetEnabledMask, in ci_enable_uvd_dpm()
4001 PPSMC_MSG_MCLKDPM_SetEnabledMask, in ci_enable_uvd_dpm()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dppsmc.h134 #define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) macro
/dragonfly/sys/dev/drm/amd/powerplay/inc/
H A Dfiji_ppsmc.h246 #define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) macro
H A Dsmu7_ppsmc.h243 #define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) macro
H A Dtonga_ppsmc.h270 #define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146) macro
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu7_hwmgr.c2644 PPSMC_MSG_MCLKDPM_SetEnabledMask, in smu7_force_dpm_highest()
2670 PPSMC_MSG_MCLKDPM_SetEnabledMask, in smu7_upload_dpm_level_enable_mask()
2713 PPSMC_MSG_MCLKDPM_SetEnabledMask, in smu7_force_dpm_lowest()
4403 PPSMC_MSG_MCLKDPM_SetEnabledMask, in smu7_force_clock_level()