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Searched refs:Q_CSR (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/netif/msk/
H A Dif_msk.c3504 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); in msk_init()
3505 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); in msk_init()
3529 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); in msk_init()
3530 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); in msk_init()
3544 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), in msk_init()
3712 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); in msk_stop()
3713 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); in msk_stop()
3716 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), in msk_stop()
3718 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); in msk_stop()
3737 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), in msk_stop()
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H A Dif_mskreg.h560 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ macro