/dragonfly/sys/dev/drm/radeon/ |
H A D | ci_smc.c | 116 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_start_smc() 124 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in ci_reset_smc() 139 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_stop_smc_clock() 148 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_start_smc_clock() 157 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_is_smc_running() 158 u32 pc_c = RREG32_SMC(SMC_PC_C); in ci_is_smc_running() 176 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0);
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H A D | si_smc.c | 115 u32 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_start_smc() 131 tmp = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_reset_smc() 145 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_stop_smc_clock() 154 u32 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_start_smc_clock() 163 u32 rst = RREG32_SMC(SMC_SYSCON_RESET_CNTL); in si_is_smc_running() 164 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_is_smc_running() 202 tmp = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_wait_for_smc_inactive()
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H A D | trinity_dpm.c | 383 value = RREG32_SMC(GFX_POWER_GATING_CNTL); in trinity_gfx_powergating_initialize() 527 value = RREG32_SMC(PM_I_CNTL_1); in trinity_gfx_dynamic_mgpg_enable() 532 value = RREG32_SMC(SMU_S_PG_CNTL); in trinity_gfx_dynamic_mgpg_enable() 537 value = RREG32_SMC(SMU_S_PG_CNTL); in trinity_gfx_dynamic_mgpg_enable() 541 value = RREG32_SMC(PM_I_CNTL_1); in trinity_gfx_dynamic_mgpg_enable() 761 u32 value = RREG32_SMC(SMU_SCLK_DPM_CNTL); in trinity_start_dpm() 890 u32 tp = RREG32_SMC(PM_TP); in trinity_setup_uvd_dpm_interval() 1013 u32 value = RREG32_SMC(SMU_SCLK_DPM_TTT); in trinity_program_ttt() 1033 u32 tp = RREG32_SMC(PM_TP); in trinity_program_sclk_dpm() 1042 value = RREG32_SMC(PM_I_CNTL_1); in trinity_program_sclk_dpm() [all …]
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H A D | ci_dpm.c | 920 tmp = RREG32_SMC(CG_THERMAL_INT); in ci_thermal_set_temperature_range() 928 tmp = RREG32_SMC(CG_THERMAL_CTRL); in ci_thermal_set_temperature_range() 1450 tmp = RREG32_SMC(GENERAL_PWRMGT); in ci_set_dpm_event_sources() 1457 tmp = RREG32_SMC(GENERAL_PWRMGT); in ci_set_dpm_event_sources() 1567 tmp = RREG32_SMC(GENERAL_PWRMGT); in ci_start_dpm() 1628 tmp = RREG32_SMC(GENERAL_PWRMGT); in ci_stop_dpm() 1909 RREG32_SMC(CG_SPLL_FUNC_CNTL); in ci_read_clock_registers() 1911 RREG32_SMC(CG_SPLL_FUNC_CNTL_2); in ci_read_clock_registers() 1913 RREG32_SMC(CG_SPLL_FUNC_CNTL_3); in ci_read_clock_registers() 1915 RREG32_SMC(CG_SPLL_FUNC_CNTL_4); in ci_read_clock_registers() [all …]
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H A D | kv_smc.c | 61 *enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0); in kv_dpm_get_enable_mask()
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H A D | kv_dpm.c | 295 data = RREG32_SMC(config_regs->offset); in kv_program_pt_config_registers() 642 u32 tmp = RREG32_SMC(GENERAL_PWRMGT); in kv_start_dpm() 657 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_start_am() 667 u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL); in kv_reset_am() 1173 thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL); in kv_enable_thermal_int() 2437 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1); in kv_program_nbps_index_settings() 2464 tmp = RREG32_SMC(CG_THERMAL_INT_CTRL); in kv_set_thermal_temperature_range() 2801 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> in kv_dpm_debugfs_print_current_performance_level() 2810 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >> in kv_dpm_debugfs_print_current_performance_level() 2824 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >> in kv_dpm_get_current_sclk()
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H A D | cik.c | 217 temp = RREG32_SMC(0xC0300E0C); in kv_get_temp() 1711 if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE) in cik_get_xclk() 9405 tmp = RREG32_SMC(cntl_reg); in cik_set_uvd_clock() 9411 if (RREG32_SMC(status_reg) & DCLK_STATUS) in cik_set_uvd_clock() 9445 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) in cik_set_vce_clocks() 9452 tmp = RREG32_SMC(CG_ECLK_CNTL); in cik_set_vce_clocks() 9458 if (RREG32_SMC(CG_ECLK_STATUS) & ECLK_STATUS) in cik_set_vce_clocks() 9732 orig = data = RREG32_SMC(THM_CLK_CNTL); in cik_program_aspm() 9738 orig = data = RREG32_SMC(MISC_CLK_CTRL); in cik_program_aspm() 9744 orig = data = RREG32_SMC(CG_CLKPIN_CNTL); in cik_program_aspm() [all …]
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H A D | radeon.h | 2552 #define RREG32_SMC(reg) tn_smc_rreg(rdev, (reg)) macro 2584 uint32_t tmp_ = RREG32_SMC(reg); \
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H A D | ni.c | 892 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff; in tn_get_temp()
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H A D | si.c | 7469 if ((RREG32_SMC(CG_VCEPLL_FUNC_CNTL) & mask) == mask) in si_vce_send_vcepll_ctlreq()
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H A D | si_dpm.c | 2750 data = RREG32_SMC(offset); in si_program_cac_config_registers()
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | cik.c | 905 rom_cntl = RREG32_SMC(ixROM_CNTL); in cik_read_disabled_bios() 1311 tmp = RREG32_SMC(cntl_reg); in cik_set_uvd_clock() 1318 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) in cik_set_uvd_clock() 1353 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) in cik_set_vce_clocks() 1360 tmp = RREG32_SMC(ixCG_ECLK_CNTL); in cik_set_vce_clocks() 1367 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) in cik_set_vce_clocks() 1644 orig = data = RREG32_SMC(ixTHM_CLK_CNTL); in cik_program_aspm() 1652 orig = data = RREG32_SMC(ixMISC_CLK_CTRL); in cik_program_aspm() 1660 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL); in cik_program_aspm() 1665 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2); in cik_program_aspm() [all …]
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H A D | vi.c | 334 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); in vi_get_xclk() 338 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL); in vi_get_xclk() 389 rom_cntl = RREG32_SMC(ixROM_CNTL); in vi_read_disabled_bios() 731 tmp = RREG32_SMC(cntl_reg); in vi_set_uvd_clock() 742 tmp = RREG32_SMC(status_reg); in vi_set_uvd_clock() 818 if (RREG32_SMC(reg_status) & status_mask) in vi_set_vce_clocks() 826 tmp = RREG32_SMC(reg_ctrl); in vi_set_vce_clocks() 832 if (RREG32_SMC(reg_status) & status_mask) in vi_set_vce_clocks() 897 return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK) in vi_get_rev_id() 1346 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0); in vi_update_rom_medium_grain_clock_gating() [all …]
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H A D | vce_v3_0.c | 374 tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) & in vce_v3_0_get_harvest_config() 378 tmp = (RREG32_SMC(ixCC_HARVEST_FUSES) & in vce_v3_0_get_harvest_config() 820 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); in vce_v3_0_get_clockgating_state() 822 data = RREG32_SMC(ixCURRENT_PG_STATUS); in vce_v3_0_get_clockgating_state()
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H A D | uvd_v6_0.c | 377 (RREG32_SMC(ixCC_HARVEST_FUSES) & CC_HARVEST_FUSES__UVD_DISABLE_MASK)) in uvd_v6_0_early_init() 1491 data = RREG32_SMC(ixCURRENT_PG_STATUS_APU); in uvd_v6_0_get_clockgating_state() 1493 data = RREG32_SMC(ixCURRENT_PG_STATUS); in uvd_v6_0_get_clockgating_state()
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H A D | amdgpu_cgs.c | 67 return RREG32_SMC(index); in amdgpu_cgs_read_ind_register()
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H A D | uvd_v5_0.c | 825 if (RREG32_SMC(ixCURRENT_PG_STATUS) & in uvd_v5_0_get_clockgating_state()
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H A D | amdgpu_debugfs.c | 400 value = RREG32_SMC(*pos); in amdgpu_debugfs_regs_smc_read()
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H A D | vce_v4_0.c | 870 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
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H A D | si_dpm.c | 2849 data = RREG32_SMC(offset); in si_program_cac_config_registers() 7512 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state() 7517 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state() 7529 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state() 7534 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT); in si_dpm_set_interrupt_state()
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H A D | amdgpu.h | 1635 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) macro
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H A D | uvd_v7_0.c | 1682 u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
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