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Searched refs:SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h1201 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT macro
H A Dsdma0_4_0_sh_mask.h1209 #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 0x0 macro