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Searched refs:SDMA0_PHASE0_QUANTUM__VALUE_MASK (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsdma_v3_0.c560 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v3_0_ctx_switch_enable()
567 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v3_0_ctx_switch_enable()
H A Dsdma_v4_0.c547 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v4_0_ctx_switch_enable()
554 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >> in sdma_v4_0_ctx_switch_enable()
/dragonfly/sys/dev/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h599 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK … macro
H A Dsdma0_4_0_sh_mask.h600 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0x00FFFF00L macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h1013 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 macro
H A Doss_2_4_sh_mask.h1103 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 macro
H A Doss_3_0_1_sh_mask.h1123 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 macro
H A Doss_3_0_sh_mask.h1629 #define SDMA0_PHASE0_QUANTUM__VALUE_MASK 0xffff00 macro