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Searched refs:SDMA0_PHASE0_QUANTUM__VALUE__SHIFT (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dsdma_v3_0.c561 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { in sdma_v3_0_ctx_switch_enable()
568 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); in sdma_v3_0_ctx_switch_enable()
576 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | in sdma_v3_0_ctx_switch_enable()
H A Dsdma_v4_0.c548 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) { in sdma_v4_0_ctx_switch_enable()
555 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT); in sdma_v4_0_ctx_switch_enable()
563 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT | in sdma_v4_0_ctx_switch_enable()
/dragonfly/sys/dev/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h596 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT … macro
H A Dsdma0_4_0_sh_mask.h597 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h1014 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
H A Doss_2_4_sh_mask.h1104 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
H A Doss_3_0_1_sh_mask.h1124 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro
H A Doss_3_0_sh_mask.h1630 #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8 macro