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Searched refs:SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h1423 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT … macro
H A Dsdma0_4_0_sh_mask.h1617 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h1192 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 macro
H A Doss_2_4_sh_mask.h1312 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 macro
H A Doss_3_0_1_sh_mask.h1762 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 macro
H A Doss_3_0_sh_mask.h2078 #define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO__ADDR__SHIFT 0x2 macro