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Searched refs:SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_sh_mask.h1507 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT … macro
H A Dsdma0_4_0_sh_mask.h1701 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h1280 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro
H A Doss_2_4_sh_mask.h1416 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro
H A Doss_3_0_1_sh_mask.h1892 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro
H A Doss_3_0_sh_mask.h2202 #define SDMA0_RLC1_RB_WPTR_POLL_CNTL__ENABLE__SHIFT 0x0 macro