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Searched refs:SPI_PS_IN_CONTROL_0 (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/radeon/reg_srcs/
H A Devergreen436 0x000286CC SPI_PS_IN_CONTROL_0
H A Dcayman422 0x000286CC SPI_PS_IN_CONTROL_0
H A Dr600427 0x000286CC SPI_PS_IN_CONTROL_0
/dragonfly/sys/dev/drm/radeon/
H A Drv770d.h530 #define SPI_PS_IN_CONTROL_0 0x286CC macro
H A Drv770.c1574 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); in rv770_gpu_init()
H A Devergreend.h1026 #define SPI_PS_IN_CONTROL_0 0x286CC macro
H A Dr600d.h451 #define SPI_PS_IN_CONTROL_0 0x286CC macro
H A Dr600.c2334 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); in r600_gpu_init()