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Searched refs:SPLL_CTL (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_dpll_mgr.c477 I915_WRITE(SPLL_CTL, pll->state.hw_state.spll); in hsw_ddi_spll_enable()
478 POSTING_READ(SPLL_CTL); in hsw_ddi_spll_enable()
497 val = I915_READ(SPLL_CTL); in hsw_ddi_spll_disable()
498 I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); in hsw_ddi_spll_disable()
499 POSTING_READ(SPLL_CTL); in hsw_ddi_spll_disable()
528 val = I915_READ(SPLL_CTL); in hsw_ddi_spll_get_hw_state()
H A Dintel_ddi.c1429 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; in hsw_ddi_clock_get()
H A Di915_reg.h8428 #define SPLL_CTL _MMIO(0x46020) macro
H A Dintel_display.c8697 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); in assert_can_disable_lcpll()