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Searched refs:UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT (Results 1 – 2 of 2) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h9020 #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT 0x00000011 macro
H A Ddce_8_0_sh_mask.h4200 #define UNIPHYCD_TPG_CONTROL__UNIPHYCD_TPG_SEL__SHIFT 0x11 macro