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Searched refs:UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h260 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK … macro
H A Duvd_5_0_sh_mask.h795 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x20 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h527 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK … macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dvcn_v1_0.c442 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK in vcn_v1_0_disable_clock_gating()
515 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK in vcn_v1_0_enable_clock_gating()