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Searched refs:UVD_SUVD_CGC_GATE__SMP_MASK (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Duvd_v6_0.c657 UVD_SUVD_CGC_GATE__SMP_MASK |
690 UVD_SUVD_CGC_GATE__SMP_MASK |
1272 UVD_SUVD_CGC_GATE__SMP_MASK | in uvd_v6_0_enable_clock_gating()
1397 UVD_SUVD_CGC_GATE__SMP_MASK |
H A Duvd_v5_0.c620 UVD_SUVD_CGC_GATE__SMP_MASK | in uvd_v5_0_enable_clock_gating()
733 UVD_SUVD_CGC_GATE__SMP_MASK |
H A Duvd_v7_0.c1596 UVD_SUVD_CGC_GATE__SMP_MASK |
1669 UVD_SUVD_CGC_GATE__SMP_MASK |
H A Dvcn_v1_0.c412 | UVD_SUVD_CGC_GATE__SMP_MASK in vcn_v1_0_disable_clock_gating()
/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h228 #define UVD_SUVD_CGC_GATE__SMP_MASK … macro
H A Duvd_5_0_sh_mask.h727 #define UVD_SUVD_CGC_GATE__SMP_MASK 0x4 macro
H A Duvd_6_0_sh_mask.h729 #define UVD_SUVD_CGC_GATE__SMP_MASK 0x4 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h431 #define UVD_SUVD_CGC_GATE__SMP_MASK … macro