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Searched refs:UVD_SUVD_CGC_GATE__SRE_H264_MASK (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Duvd_v6_0.c660 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
693 UVD_SUVD_CGC_GATE__SRE_H264_MASK |
1275 UVD_SUVD_CGC_GATE__SRE_H264_MASK | in uvd_v6_0_enable_clock_gating()
H A Dvcn_v1_0.c415 | UVD_SUVD_CGC_GATE__SRE_H264_MASK in vcn_v1_0_disable_clock_gating()
/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h231 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK … macro
H A Duvd_5_0_sh_mask.h733 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20 macro
H A Duvd_6_0_sh_mask.h735 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x20 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h434 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK … macro