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Searched refs:UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h755 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2 macro
H A Duvd_6_0_sh_mask.h753 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x2 macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h484 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK … macro