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Searched refs:VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h9391 #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x0000007fL macro
H A Ddce_8_0_sh_mask.h1369 #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f macro
H A Ddce_10_0_sh_mask.h11787 #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f macro
H A Ddce_11_0_sh_mask.h11599 #define VGA25_PPLL_POST_DIV__VGA25_PPLL_POST_DIV_PIXCLK_MASK 0x7f macro