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Searched refs:VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h9489 #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x00000002L macro
H A Ddce_8_0_sh_mask.h11111 #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2 macro
H A Ddce_10_0_sh_mask.h11495 #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2 macro
H A Ddce_11_0_sh_mask.h11307 #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2 macro
H A Ddce_11_2_sh_mask.h12561 #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK 0x2 macro
H A Ddce_12_0_sh_mask.h2137 #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h1687 #define VGA_INTERRUPT_STATUS__VGA_REG_ACCESS_INT_STATUS_MASK … macro