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Searched refs:WREG32_PLL (Results 1 – 13 of 13) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dradeon_clocks.c402 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
408 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
414 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
430 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
434 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
440 WREG32_PLL(RADEON_SPLL_CNTL, tmp); in radeon_legacy_set_engine_clock()
461 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_engine_clock()
492 WREG32_PLL(RADEON_SCLK_CNTL, tmp); in radeon_legacy_set_clock_gating()
550 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
643 WREG32_PLL(R300_SCLK_CNTL2, tmp); in radeon_legacy_set_clock_gating()
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H A Drs600.c262 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length); in rs600_pm_misc()
274 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl); in rs600_pm_misc()
281 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl); in rs600_pm_misc()
289 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl); in rs600_pm_misc()
296 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl); in rs600_pm_misc()
H A Dradeon_legacy_crtc.c894 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl); in radeon_set_pll()
919 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); in radeon_set_pll()
999 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl); in radeon_set_pll()
1025 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); in radeon_set_pll()
H A Dradeon_legacy_tv.c284 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B); in radeon_wait_pll_lock()
293 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test); in radeon_wait_pll_lock()
771 WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl); in radeon_legacy_tv_mode_set()
H A Dradeon_legacy_encoders.c121 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); in radeon_legacy_lvds_update()
667 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); in radeon_legacy_primary_dac_detect()
710 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); in radeon_legacy_primary_dac_detect()
1602 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); in radeon_legacy_tv_dac_detect()
1676 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); in radeon_legacy_tv_dac_detect()
H A Dr520.c87 WREG32_PLL(0x000D, tmp); in r520_gpu_init()
H A Drv515.c165 WREG32_PLL(0x000D, tmp); in rv515_gpu_init()
503 WREG32_PLL(R_00000F_CP_DYN_CNTL, in rv515_clock_startup()
505 WREG32_PLL(R_000011_E2_DYN_CNTL, in rv515_clock_startup()
507 WREG32_PLL(R_000013_IDCT_DYN_CNTL, in rv515_clock_startup()
H A Dr420.c201 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl); in r420_clock_resume()
H A Dradeon_combios.c2983 WREG32_PLL(reg, val); in radeon_combios_external_tmds_setup()
3100 WREG32_PLL(addr, val); in combios_parse_pll_table()
3113 WREG32_PLL(addr, tmp); in combios_parse_pll_table()
3152 WREG32_PLL(RADEON_MCLK_CNTL, in combios_parse_pll_table()
3156 WREG32_PLL in combios_parse_pll_table()
H A Dr100.c420 WREG32_PLL(SCLK_CNTL, sclk_cntl); in r100_pm_misc()
421 WREG32_PLL(SCLK_CNTL2, sclk_cntl2); in r100_pm_misc()
422 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl); in r100_pm_misc()
2702 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); in r100_set_common_regs()
3897 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); in r100_clock_startup()
H A Dr300.c1365 WREG32_PLL(R_00000D_SCLK_CNTL, tmp); in r300_clock_startup()
H A Dradeon.h2545 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) macro
2580 WREG32_PLL(reg, tmp_); \
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Damdgpu.h1661 WREG32_PLL(reg, tmp_); \