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Searched refs:WREG32_SMC (Results 1 – 19 of 19) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Dtrinity_smc.c67 WREG32_SMC(SMU_SCRATCH0, 1); in trinity_dpm_config()
69 WREG32_SMC(SMU_SCRATCH0, 0); in trinity_dpm_config()
76 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_force_state()
83 WREG32_SMC(SMU_SCRATCH0, n); in trinity_dpm_n_levels_disabled()
H A Dtrinity_dpm.c388 WREG32_SMC(GFX_POWER_GATING_CNTL, value); in trinity_gfx_powergating_initialize()
530 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable()
535 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable()
539 WREG32_SMC(SMU_S_PG_CNTL, value); in trinity_gfx_dynamic_mgpg_enable()
543 WREG32_SMC(PM_I_CNTL_1, value); in trinity_gfx_dynamic_mgpg_enable()
765 WREG32_SMC(SMU_SCLK_DPM_CNTL, value); in trinity_start_dpm()
898 WREG32_SMC(SMU_UVD_DPM_CNTL, val); in trinity_setup_uvd_dpm_interval()
1018 WREG32_SMC(SMU_SCLK_DPM_TTT, value); in trinity_program_ttt()
1027 WREG32_SMC(SMU_SCLK_DPM_TT_CNTL, value); in trinity_enable_att()
1045 WREG32_SMC(PM_I_CNTL_1, value); in trinity_program_sclk_dpm()
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H A Dci_smc.c119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_start_smc()
127 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in ci_reset_smc()
143 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_stop_smc_clock()
152 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in ci_start_smc_clock()
H A Dsi_smc.c119 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_start_smc()
133 WREG32_SMC(SMC_SYSCON_RESET_CNTL, tmp); in si_reset_smc()
149 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_stop_smc_clock()
158 WREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0, tmp); in si_start_smc_clock()
H A Dci_dpm.c984 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
988 WREG32_SMC(CG_FDO_CTRL2, tmp); in ci_fan_ctrl_set_static_mode()
1162 WREG32_SMC(CG_FDO_CTRL0, tmp); in ci_fan_ctrl_set_fan_speed_percent()
2117 WREG32_SMC(CG_FTV_0, 0); in ci_clear_vc()
2118 WREG32_SMC(CG_FTV_1, 0); in ci_clear_vc()
2119 WREG32_SMC(CG_FTV_2, 0); in ci_clear_vc()
2120 WREG32_SMC(CG_FTV_3, 0); in ci_clear_vc()
2121 WREG32_SMC(CG_FTV_4, 0); in ci_clear_vc()
2122 WREG32_SMC(CG_FTV_5, 0); in ci_clear_vc()
2123 WREG32_SMC(CG_FTV_6, 0); in ci_clear_vc()
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H A Dkv_dpm.c403 WREG32_SMC(LCAC_SX0_OVR_SEL, 0);
404 WREG32_SMC(LCAC_SX0_OVR_VAL, 0);
407 WREG32_SMC(LCAC_MC0_OVR_SEL, 0);
408 WREG32_SMC(LCAC_MC0_OVR_VAL, 0);
411 WREG32_SMC(LCAC_MC1_OVR_SEL, 0);
412 WREG32_SMC(LCAC_MC1_OVR_VAL, 0);
415 WREG32_SMC(LCAC_MC2_OVR_SEL, 0);
416 WREG32_SMC(LCAC_MC2_OVR_VAL, 0);
419 WREG32_SMC(LCAC_MC3_OVR_SEL, 0);
527 WREG32_SMC(CG_FTV_0, 0); in kv_clear_vc()
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H A Dcik.c9408 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock()
9455 WREG32_SMC(CG_ECLK_CNTL, tmp); in cik_set_vce_clocks()
9736 WREG32_SMC(THM_CLK_CNTL, data); in cik_program_aspm()
9742 WREG32_SMC(MISC_CLK_CTRL, data); in cik_program_aspm()
9747 WREG32_SMC(CG_CLKPIN_CNTL, data); in cik_program_aspm()
9752 WREG32_SMC(CG_CLKPIN_CNTL_2, data); in cik_program_aspm()
9758 WREG32_SMC(MPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
H A Dsi.c5452 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0); in si_enable_uvd_mgcg()
5453 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0); in si_enable_uvd_mgcg()
5464 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_0, 0xffffffff); in si_enable_uvd_mgcg()
5465 WREG32_SMC(SMC_CG_IND_START + CG_CGTT_LOCAL_1, 0xffffffff); in si_enable_uvd_mgcg()
H A Dradeon.h2553 #define WREG32_SMC(reg, v) tn_smc_wreg(rdev, (reg), (v)) macro
2587 WREG32_SMC(reg, tmp_); \
H A Dsi_dpm.c2764 WREG32_SMC(offset, data); in si_program_cac_config_registers()
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dcik.c920 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in cik_read_disabled_bios()
931 WREG32_SMC(ixROM_CNTL, rom_cntl); in cik_read_disabled_bios()
1315 WREG32_SMC(cntl_reg, tmp); in cik_set_uvd_clock()
1364 WREG32_SMC(ixCG_ECLK_CNTL, tmp); in cik_set_vce_clocks()
1650 WREG32_SMC(ixTHM_CLK_CNTL, data); in cik_program_aspm()
1658 WREG32_SMC(ixMISC_CLK_CTRL, data); in cik_program_aspm()
1663 WREG32_SMC(ixCG_CLKPIN_CNTL, data); in cik_program_aspm()
1668 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); in cik_program_aspm()
1674 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); in cik_program_aspm()
H A Dvi.c404 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); in vi_read_disabled_bios()
415 WREG32_SMC(ixROM_CNTL, rom_cntl); in vi_read_disabled_bios()
739 WREG32_SMC(cntl_reg, tmp); in vi_set_uvd_clock()
829 WREG32_SMC(reg_ctrl, tmp); in vi_set_vce_clocks()
1356 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data); in vi_update_rom_medium_grain_clock_gating()
H A Damdgpu_cgs.c95 return WREG32_SMC(index, value); in amdgpu_cgs_write_ind_register()
H A Damdgpu_debugfs.c443 WREG32_SMC(*pos, value); in amdgpu_debugfs_regs_smc_write()
H A Dvce_v4_0.c877 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
H A Dsi_dpm.c2863 WREG32_SMC(offset, data); in si_program_cac_config_registers()
7514 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7519 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7531 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
7536 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int); in si_dpm_set_interrupt_state()
H A Damdgpu.h1636 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) macro
H A Duvd_v7_0.c1691 WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
H A Dgfx_v8_0.c790 WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); in gfx_v8_0_init_golden_registers()