| /dragonfly/sys/dev/drm/amd/amdgpu/ |
| H A D | amdgpu_device.c | 526 adev->doorbell.base = pci_resource_start(adev->pdev, 2); in amdgpu_device_doorbell_init()
527 adev->doorbell.size = pci_resource_len(adev->pdev, 2); in amdgpu_device_doorbell_init()
534 adev->doorbell.ptr = ioremap(adev->doorbell.base, in amdgpu_device_doorbell_init()
599 &adev->wb.wb_obj, (u64 *)&adev->wb.gpu_addr, in amdgpu_device_wb_init()
607 memset(&adev->wb.used, 0, sizeof(adev->wb.used)); in amdgpu_device_wb_init()
1697 return !!memcmp(adev->gart.ptr, adev->reset_magic, in amdgpu_device_check_vram_lost()
2196 r = adev->ip_blocks[i].version->funcs->resume(adev); in amdgpu_device_ip_resume_phase2()
2421 adev->rmmio_size = pci_resource_len(adev->pdev, 5); in amdgpu_device_init()
2424 adev->rmmio_size = pci_resource_len(adev->pdev, 2); in amdgpu_device_init()
2427 adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size); in amdgpu_device_init()
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| H A D | vi.c | 987 adev->rev_id = vi_get_rev_id(adev); in vi_common_early_init()
1014 adev->external_rev_id = adev->rev_id + 0x3c; in vi_common_early_init()
1031 adev->external_rev_id = adev->rev_id + 0x14; in vi_common_early_init()
1054 adev->external_rev_id = adev->rev_id + 0x5A; in vi_common_early_init()
1077 adev->external_rev_id = adev->rev_id + 0x50; in vi_common_early_init()
1100 adev->external_rev_id = adev->rev_id + 0x64; in vi_common_early_init()
1124 adev->external_rev_id = adev->rev_id + 0x6E; in vi_common_early_init()
1151 adev->external_rev_id = adev->rev_id + 0x1; in vi_common_early_init()
1174 adev->external_rev_id = adev->rev_id + 0x61; in vi_common_early_init()
1612 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) in vi_set_ip_blocks()
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| H A D | soc15.c | 76 data = adev->nbio_funcs->get_pcie_data_offset(adev); in soc15_pcie_rreg()
91 data = adev->nbio_funcs->get_pcie_data_offset(adev); in soc15_pcie_wreg()
203 return adev->nbio_funcs->get_memsize(adev); in soc15_get_config_memsize()
406 u32 memsize = adev->nbio_funcs->get_memsize(adev); in soc15_asic_reset()
516 adev->nbio_funcs->detect_hw_virt(adev); in soc15_set_ip_blocks()
573 return adev->nbio_funcs->get_rev_id(adev); in soc15_get_rev_id()
578 adev->nbio_funcs->hdp_flush(adev, ring); in soc15_flush_hdp()
632 adev->rev_id = soc15_get_rev_id(adev); in soc15_common_early_init()
678 adev->external_rev_id = adev->rev_id + 0x14; in soc15_common_early_init()
700 adev->external_rev_id = adev->rev_id + 0x28; in soc15_common_early_init()
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| H A D | amdgpu_ih.c | 43 r = amdgpu_bo_create_kernel(adev, adev->irq.ih.ring_size, in amdgpu_ih_ring_alloc()
75 adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1; in amdgpu_ih_ring_init()
84 adev->irq.ih.ring = pci_alloc_consistent(adev->pdev, in amdgpu_ih_ring_init()
95 r = amdgpu_device_wb_get(adev, &adev->irq.ih.wptr_offs); in amdgpu_ih_ring_init()
101 r = amdgpu_device_wb_get(adev, &adev->irq.ih.rptr_offs); in amdgpu_ih_ring_init()
103 amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs); in amdgpu_ih_ring_init()
136 amdgpu_device_wb_free(adev, adev->irq.ih.wptr_offs); in amdgpu_ih_ring_fini()
137 amdgpu_device_wb_free(adev, adev->irq.ih.rptr_offs); in amdgpu_ih_ring_fini()
154 if (!adev->irq.ih.enabled || adev->shutdown) in amdgpu_ih_process()
174 adev->irq.ih.rptr &= adev->irq.ih.ptr_mask; in amdgpu_ih_process()
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| H A D | gmc_v9_0.c | 374 struct amdgpu_device *adev = ring->adev; in gmc_v9_0_emit_flush_gpu_tlb() local
399 struct amdgpu_device *adev = ring->adev; in gmc_v9_0_emit_pasid_mapping() local
692 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v9_0_late_init()
701 amdgpu_device_vram_location(adev, &adev->gmc, base); in gmc_v9_0_vram_gtt_location()
737 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; in gmc_v9_0_mc_init()
750 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v9_0_mc_init()
754 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v9_0_mc_init()
775 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); in gmc_v9_0_mc_init()
858 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) { in gmc_v9_0_sw_init()
1065 adev->nbio_funcs->hdp_flush(adev, NULL); in gmc_v9_0_gart_enable()
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| H A D | amdgpu_pm.c | 80 amdgpu_dpm_enable_bapm(adev, adev->pm.ac_power); in amdgpu_pm_acpi_event_handler()
776 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
860 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1707 if (adev->pm.dpm.user_state != adev->pm.dpm.state) { in amdgpu_dpm_change_power_state_locked()
1711 adev->pm.dpm.state = adev->pm.dpm.user_state; in amdgpu_dpm_change_power_state_locked()
1723 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps); in amdgpu_dpm_change_power_state_locked()
1725 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps); in amdgpu_dpm_change_power_state_locked()
1738 …if (0 != amdgpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &e… in amdgpu_dpm_change_power_state_locked()
1748 adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs; in amdgpu_dpm_change_power_state_locked()
1828 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]); in amdgpu_pm_print_power_states()
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| H A D | amdgpu_gart.c | 75 adev->dummy_page_addr = pci_map_page(adev->pdev, dummy_page, 0, in amdgpu_gart_dummy_page_init()
77 if (pci_dma_mapping_error(adev->pdev, adev->dummy_page_addr)) { in amdgpu_gart_dummy_page_init()
96 pci_unmap_page(adev->pdev, adev->dummy_page_addr, in amdgpu_gart_dummy_page_fini()
126 r = amdgpu_bo_create(adev, &bp, &adev->gart.robj); in amdgpu_gart_table_vram_alloc()
156 r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr); in amdgpu_gart_table_vram_pin()
160 adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.robj); in amdgpu_gart_table_vram_pin()
245 amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr, in amdgpu_gart_unbind()
325 if (!adev->gart.ptr) in amdgpu_gart_bind()
363 adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE; in amdgpu_gart_init()
364 adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE; in amdgpu_gart_init()
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| H A D | tonga_ih.c | 86 adev->irq.ih.rptr = 0; in tonga_ih_disable_interrupts()
140 wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); in tonga_ih_irq_init()
142 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in tonga_ih_irq_init()
201 wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]); in tonga_ih_get_wptr()
203 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in tonga_ih_get_wptr()
212 wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask); in tonga_ih_get_wptr()
213 adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask; in tonga_ih_get_wptr()
292 adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; in tonga_ih_set_rptr()
294 adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; in tonga_ih_set_rptr()
295 WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr); in tonga_ih_set_rptr()
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| H A D | amdgpu_dpm.h | 243 ((adev)->powerplay.pp_funcs->pre_set_power_state((adev)->powerplay.pp_handle))
246 ((adev)->powerplay.pp_funcs->set_power_state((adev)->powerplay.pp_handle))
258 ((adev)->powerplay.pp_funcs->vblank_too_short((adev)->powerplay.pp_handle))
261 ((adev)->powerplay.pp_funcs->enable_bapm((adev)->powerplay.pp_handle, (e)))
282 ((adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)))
285 ((adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)))
297 ((adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table))
309 ((adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle))
312 ((adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value))
315 ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
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| H A D | gfx_v9_0.c | 341 struct amdgpu_device *adev = ring->adev; in gfx_v9_0_ring_test_ring() local
385 struct amdgpu_device *adev = ring->adev; in gfx_v9_0_ring_test_ib() local
2341 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v9_0_cp_gfx_load_microcode()
2584 struct amdgpu_device *adev = ring->adev; in gfx_v9_0_kiq_setting() local
2688 struct amdgpu_device *adev = ring->adev; in gfx_v9_0_mqd_init() local
2826 struct amdgpu_device *adev = ring->adev; in gfx_v9_0_kiq_init_register() local
2931 struct amdgpu_device *adev = ring->adev; in gfx_v9_0_kiq_fini_register() local
2970 struct amdgpu_device *adev = ring->adev; in gfx_v9_0_kiq_init_queue() local
3010 struct amdgpu_device *adev = ring->adev; in gfx_v9_0_kcq_init_queue() local
3394 struct amdgpu_device *adev = ring->adev; in gfx_v9_0_ring_emit_gds_switch() local
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| H A D | amdgpu_cgs.c | 249 if (!adev->pm.fw) { in amdgpu_cgs_get_firmware_info()
331 if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) || in amdgpu_cgs_get_firmware_info()
332 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) || in amdgpu_cgs_get_firmware_info()
333 ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87)) || in amdgpu_cgs_get_firmware_info()
334 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD1)) || in amdgpu_cgs_get_firmware_info()
335 ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD3))) { in amdgpu_cgs_get_firmware_info()
342 if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) || in amdgpu_cgs_get_firmware_info()
343 ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) { in amdgpu_cgs_get_firmware_info()
437 err = request_firmware(&adev->pm.fw, fw_name, adev->dev); in amdgpu_cgs_get_firmware_info()
447 adev->pm.fw = NULL; in amdgpu_cgs_get_firmware_info()
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| H A D | cik.c | 1775 adev->rev_id = cik_get_rev_id(adev); in cik_common_early_init()
1779 adev->cg_flags = in cik_common_early_init()
1796 adev->pg_flags = 0; in cik_common_early_init()
1797 adev->external_rev_id = adev->rev_id + 0x14; in cik_common_early_init()
1800 adev->cg_flags = in cik_common_early_init()
1816 adev->pg_flags = 0; in cik_common_early_init()
1820 adev->cg_flags = in cik_common_early_init()
1835 adev->pg_flags = in cik_common_early_init()
1856 adev->cg_flags = in cik_common_early_init()
1871 adev->pg_flags = in cik_common_early_init()
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| H A D | amdgpu_virt.c | 100 *bo_va = amdgpu_vm_bo_add(adev, vm, adev->virt.csa_obj); in amdgpu_map_static_csa()
111 amdgpu_vm_bo_rmv(adev, *bo_va); in amdgpu_map_static_csa()
122 amdgpu_vm_bo_rmv(adev, *bo_va); in amdgpu_map_static_csa()
134 adev->mode_info.num_crtc = 1; in amdgpu_virt_init_setting()
136 adev->cg_flags = 0; in amdgpu_virt_init_setting()
137 adev->pg_flags = 0; in amdgpu_virt_init_setting()
187 return adev->wb.wb[adev->virt.reg_val_offs]; in amdgpu_virt_kiq_rreg()
340 if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr) in amdgpu_virt_alloc_mm_table()
345 &adev->virt.mm_table.bo, in amdgpu_virt_alloc_mm_table()
367 if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr) in amdgpu_virt_free_mm_table()
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| H A D | amdgpu_irq.c | 108 if (!amdgpu_sriov_vf(adev)) in amdgpu_irq_reset_work_func()
214 adev->irq.msi_enabled = (adev->ddev->pdev->_irq_type == PCI_INTR_TYPE_MSI); in amdgpu_irq_init()
217 if (amdgpu_msi_ok(adev)) { in amdgpu_irq_init()
233 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc); in amdgpu_irq_init()
244 adev->irq.installed = true; in amdgpu_irq_init()
245 r = drm_irq_install(adev->ddev, adev->ddev->pdev->irq); in amdgpu_irq_init()
272 if (adev->irq.installed) { in amdgpu_irq_fini()
623 if (!adev->irq.domain) { in amdgpu_irq_add_domain()
643 if (adev->irq.domain) { in amdgpu_irq_remove_domain()
645 adev->irq.domain = NULL; in amdgpu_irq_remove_domain()
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| H A D | vega10_ih.c | 73 adev->irq.ih.rptr = 0; in vega10_ih_disable_interrupts()
98 adev->nbio_funcs->ih_control(adev); in vega10_ih_irq_init()
128 wptr_off = adev->irq.ih.rb_dma_addr + (adev->irq.ih.wptr_offs * 4); in vega10_ih_irq_init()
130 wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4); in vega10_ih_irq_init()
149 adev->nbio_funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell, in vega10_ih_irq_init()
199 wptr = le32_to_cpu(adev->irq.ih.ring[adev->irq.ih.wptr_offs]); in vega10_ih_get_wptr()
201 wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]); in vega10_ih_get_wptr()
365 adev->irq.ih.ring[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; in vega10_ih_set_rptr()
367 adev->wb.wb[adev->irq.ih.rptr_offs] = adev->irq.ih.rptr; in vega10_ih_set_rptr()
368 WDOORBELL32(adev->irq.ih.doorbell_index, adev->irq.ih.rptr); in vega10_ih_set_rptr()
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| H A D | gmc_v8_0.c | 272 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v8_0_init_microcode()
435 amdgpu_device_vram_location(adev, &adev->gmc, base); in gmc_v8_0_vram_gtt_location()
578 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v8_0_mc_init()
579 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v8_0_mc_init()
584 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v8_0_mc_init()
589 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v8_0_mc_init()
591 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; in gmc_v8_0_mc_init()
614 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); in gmc_v8_0_mc_init()
960 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v8_0_gart_init()
1069 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v8_0_late_init()
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| H A D | gmc_v7_0.c | 155 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v7_0_init_microcode()
244 amdgpu_device_vram_location(adev, &adev->gmc, base); in gmc_v7_0_vram_gtt_location()
376 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v7_0_mc_init()
377 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v7_0_mc_init()
382 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v7_0_mc_init()
387 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v7_0_mc_init()
389 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; in gmc_v7_0_mc_init()
412 gmc_v7_0_vram_gtt_location(adev, &adev->gmc); in gmc_v7_0_mc_init()
716 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v7_0_gart_init()
951 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v7_0_late_init()
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| H A D | amdgpu_amdkfd.c | 114 adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev, in amdgpu_amdkfd_device_probe()
155 if (adev->kfd) { in amdgpu_amdkfd_device_init()
221 if (adev->kfd) { in amdgpu_amdkfd_device_fini()
223 adev->kfd = NULL; in amdgpu_amdkfd_device_fini()
230 if (adev->kfd) in amdgpu_amdkfd_interrupt()
236 if (adev->kfd) in amdgpu_amdkfd_suspend()
244 if (adev->kfd) in amdgpu_amdkfd_resume()
254 if (adev->kfd) in amdgpu_amdkfd_pre_reset()
264 if (adev->kfd) in amdgpu_amdkfd_post_reset()
400 return adev->gfx.funcs->get_gpu_clock_counter(adev); in get_gpu_clock_counter()
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| H A D | amdgpu_bios.c | 99 adev->bios = NULL; in igp_read_bios_from_vram()
107 if (!adev->bios) { in igp_read_bios_from_vram()
116 kfree(adev->bios); in igp_read_bios_from_vram()
128 adev->bios = NULL; in amdgpu_read_bios()
145 kfree(adev->bios); in amdgpu_read_bios()
175 if (!adev->bios) { in amdgpu_read_bios_from_rom()
182 amdgpu_asic_read_bios_from_rom(adev, adev->bios, len); in amdgpu_read_bios_from_rom()
200 adev->bios = NULL; in amdgpu_read_platform_bios()
206 if (!adev->bios) in amdgpu_read_platform_bios()
223 kfree(adev->bios); in amdgpu_read_platform_bios()
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| H A D | amdgpu_kms.c | 53 if (adev == NULL) in amdgpu_driver_unload_kms()
56 if (adev->rmmio == NULL) in amdgpu_driver_unload_kms()
59 if (amdgpu_sriov_vf(adev)) in amdgpu_driver_unload_kms()
69 amdgpu_acpi_fini(adev); in amdgpu_driver_unload_kms()
71 amdgpu_device_fini(adev); in amdgpu_driver_unload_kms()
74 kfree(adev); in amdgpu_driver_unload_kms()
93 if (adev == NULL) { in amdgpu_driver_load_kms()
98 flags, dev, adev); in amdgpu_driver_load_kms()
1063 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); in amdgpu_enable_vblank_kms()
1079 amdgpu_irq_put(adev, &adev->crtc_irq, idx); in amdgpu_disable_vblank_kms()
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| H A D | amdgpu_acp.c | 99 adev->acp.parent = adev->dev; in acp_sw_init()
297 if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289) in acp_hw_init()
312 adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device; in acp_hw_init()
402 adev->acp.acp_res[4].end = adev->acp.acp_res[4].start; in acp_hw_init()
406 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; in acp_hw_init()
407 adev->acp.acp_cell[0].platform_data = &adev->asic_type; in acp_hw_init()
408 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); in acp_hw_init()
412 adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1]; in acp_hw_init()
418 adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2]; in acp_hw_init()
424 adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3]; in acp_hw_init()
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| H A D | amdgpu.h | 1698 struct amdgpu_device *adev = ring->adev; in amdgpu_get_sdma_instance() local
1715 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) argument
1716 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) argument
1719 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) argument
1720 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) argument
1726 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) argument
1728 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) argument
1761 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) argument
1762 #define amdgpu_ih_prescreen_iv(adev) (adev)->irq.ih_funcs->prescreen_iv((adev)) argument
1763 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) argument
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| H A D | mxgpu_ai.c | 153 r = xgpu_ai_poll_ack(adev); in xgpu_ai_mailbox_trans_msg()
252 adev->in_gpu_reset = 1; in xgpu_ai_mailbox_flr_work()
264 adev->in_gpu_reset = 0; in xgpu_ai_mailbox_flr_work()
334 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 135, &adev->virt.rcv_irq); in xgpu_ai_mailbox_add_irq_id()
338 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF, 138, &adev->virt.ack_irq); in xgpu_ai_mailbox_add_irq_id()
340 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_add_irq_id()
351 r = amdgpu_irq_get(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_get_irq()
354 r = amdgpu_irq_get(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_get_irq()
356 amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0); in xgpu_ai_mailbox_get_irq()
367 amdgpu_irq_put(adev, &adev->virt.ack_irq, 0); in xgpu_ai_mailbox_put_irq()
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| H A D | gfx_v8_0.c | 835 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_ring_test_ring() local
879 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_ring_test_ib() local
4295 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw) in gfx_v8_0_cp_gfx_load_microcode()
4593 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_kiq_setting() local
4713 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_mqd_init() local
4895 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_kiq_init_queue() local
4934 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_kcq_init_queue() local
6291 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_ring_get_wptr_gfx() local
6302 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_ring_set_wptr_gfx() local
6491 struct amdgpu_device *adev = ring->adev; in gfx_v8_0_ring_set_wptr_compute() local
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| H A D | sdma_v4_0.c | 236 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev); in sdma_v4_0_init_microcode()
297 struct amdgpu_device *adev = ring->adev; in sdma_v4_0_ring_get_wptr() local
329 struct amdgpu_device *adev = ring->adev; in sdma_v4_0_ring_set_wptr() local
433 struct amdgpu_device *adev = ring->adev; in sdma_v4_0_ring_emit_hdp_flush() local
443 adev->nbio_funcs->get_hdp_flush_done_offset(adev), in sdma_v4_0_ring_emit_hdp_flush()
444 adev->nbio_funcs->get_hdp_flush_req_offset(adev), in sdma_v4_0_ring_emit_hdp_flush()
685 adev->nbio_funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, in sdma_v4_0_gfx_resume()
923 struct amdgpu_device *adev = ring->adev; in sdma_v4_0_ring_test_ring() local
984 struct amdgpu_device *adev = ring->adev; in sdma_v4_0_ring_test_ib() local
1743 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring; in sdma_v4_0_set_buffer_funcs()
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