/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | vce_v3_0.c | 306 if (adev->asic_type >= CHIP_STONEY) in vce_v3_0_start() 343 if (adev->asic_type >= CHIP_STONEY) in vce_v3_0_stop() 369 if ((adev->asic_type == CHIP_FIJI) || in vce_v3_0_get_harvest_config() 370 (adev->asic_type == CHIP_STONEY)) in vce_v3_0_get_harvest_config() 390 if ((adev->asic_type == CHIP_POLARIS10) || in vce_v3_0_get_harvest_config() 391 (adev->asic_type == CHIP_POLARIS11) || in vce_v3_0_get_harvest_config() 392 (adev->asic_type == CHIP_POLARIS12) || in vce_v3_0_get_harvest_config() 393 (adev->asic_type == CHIP_VEGAM)) in vce_v3_0_get_harvest_config() 546 if (adev->asic_type >= CHIP_STONEY) { in vce_v3_0_mc_resume() 947 if (adev->asic_type >= CHIP_STONEY) { in vce_v3_0_set_ring_funcs()
|
H A D | amdgpu_acp.c | 302 if (adev->asic_type != CHIP_STONEY) { in acp_hw_init() 337 switch (adev->asic_type) { in acp_hw_init() 349 switch (adev->asic_type) { in acp_hw_init() 366 switch (adev->asic_type) { in acp_hw_init() 407 adev->acp.acp_cell[0].platform_data = &adev->asic_type; in acp_hw_init() 408 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); in acp_hw_init() 433 if (adev->asic_type != CHIP_STONEY) { in acp_hw_init()
|
H A D | gmc_v9_0.c | 679 if (adev->asic_type == CHIP_VEGA10 && !amdgpu_sriov_vf(adev)) { in gmc_v9_0_late_init() 760 switch (adev->asic_type) { in gmc_v9_0_mc_init() 817 switch (adev->asic_type) { in gmc_v9_0_get_vbios_fb_size() 856 switch (adev->asic_type) { in gmc_v9_0_sw_init() 981 switch (adev->asic_type) { in gmc_v9_0_init_golden_registers() 1012 if (adev->asic_type == CHIP_RAVEN) in gmc_v9_0_restore_registers() 1039 switch (adev->asic_type) { in gmc_v9_0_gart_enable() 1114 if (adev->asic_type == CHIP_RAVEN) in gmc_v9_0_save_registers()
|
H A D | soc15.c | 210 if (adev->asic_type == CHIP_RAVEN) in soc15_get_xclk() 492 switch (adev->asic_type) { in soc15_set_ip_blocks() 507 else if (adev->asic_type == CHIP_VEGA20) in soc15_set_ip_blocks() 512 if (adev->asic_type == CHIP_VEGA20) in soc15_set_ip_blocks() 521 switch (adev->asic_type) { in soc15_set_ip_blocks() 528 if (adev->asic_type != CHIP_VEGA20) { in soc15_set_ip_blocks() 634 switch (adev->asic_type) { in soc15_common_early_init() 913 switch (adev->asic_type) { in soc15_common_set_clockgating_state()
|
H A D | amdgpu_device.c | 514 if (adev->asic_type < CHIP_BONAIRE) { in amdgpu_device_doorbell_init() 766 if (adev->asic_type >= CHIP_BONAIRE) in amdgpu_device_resize_fb_bar() 817 if (adev->asic_type == CHIP_FIJI) { in amdgpu_device_need_post() 837 if (adev->asic_type >= CHIP_BONAIRE) in amdgpu_device_need_post() 1373 switch (adev->asic_type) { in amdgpu_device_parse_gpu_info_fw() 1483 switch (adev->asic_type) { in amdgpu_device_ip_early_init() 1493 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) in amdgpu_device_ip_early_init() 1520 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII)) in amdgpu_device_ip_early_init() 1534 if (adev->asic_type == CHIP_RAVEN) in amdgpu_device_ip_early_init() 2264 switch (asic_type) { in amdgpu_device_asic_has_dc_support() [all …]
|
H A D | nbio_v7_0.c | 45 if (adev->asic_type == CHIP_VEGA20) in nbio_v7_0_get_rev_id() 89 if (adev->asic_type == CHIP_VEGA20) in nbio_v7_0_sdma_doorbell_range() 149 if (adev->asic_type == CHIP_VEGA20) in nbio_v7_0_update_medium_grain_clock_gating()
|
H A D | mmhub_v1_0.c | 624 if (adev->asic_type != CHIP_RAVEN) { in mmhub_v1_0_update_medium_grain_clock_gating() 640 if (adev->asic_type != CHIP_RAVEN) in mmhub_v1_0_update_medium_grain_clock_gating() 657 if (adev->asic_type != CHIP_RAVEN) in mmhub_v1_0_update_medium_grain_clock_gating() 670 if (adev->asic_type != CHIP_RAVEN) in mmhub_v1_0_update_medium_grain_clock_gating() 676 if (adev->asic_type != CHIP_RAVEN && def2 != data2) in mmhub_v1_0_update_medium_grain_clock_gating() 735 switch (adev->asic_type) { in mmhub_v1_0_set_clockgating()
|
H A D | amdgpu_uvd.c | 133 switch (adev->asic_type) { in amdgpu_uvd_sw_init() 210 if (adev->asic_type < CHIP_VEGA20) { in amdgpu_uvd_sw_init() 231 if ((adev->asic_type == CHIP_POLARIS10 || in amdgpu_uvd_sw_init() 232 adev->asic_type == CHIP_POLARIS11) && in amdgpu_uvd_sw_init() 276 switch (adev->asic_type) { in amdgpu_uvd_sw_init() 290 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; in amdgpu_uvd_sw_init() 353 if (adev->asic_type < CHIP_POLARIS10) { in amdgpu_uvd_suspend() 1048 if (adev->asic_type >= CHIP_VEGA10) { in amdgpu_uvd_send_msg()
|
H A D | gfx_v8_0.c | 731 switch (adev->asic_type) { in gfx_v8_0_init_golden_registers() 974 switch (adev->asic_type) { in gfx_v8_0_init_microcode() 1006 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { in gfx_v8_0_init_microcode() 1026 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { in gfx_v8_0_init_microcode() 1047 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { in gfx_v8_0_init_microcode() 1127 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { in gfx_v8_0_init_microcode() 1149 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { in gfx_v8_0_init_microcode() 1791 switch (adev->asic_type) { in gfx_v8_0_gpu_early_init() 2031 switch (adev->asic_type) { in gfx_v8_0_sw_init() 2242 switch (adev->asic_type) { in gfx_v8_0_tiling_mode_table_init() [all …]
|
H A D | gmc_v8_0.c | 127 switch (adev->asic_type) { in gmc_v8_0_init_golden_registers() 224 switch (adev->asic_type) { in gmc_v8_0_init_microcode() 595 switch (adev->asic_type) { in gmc_v8_0_mc_init() 1106 if ((adev->asic_type == CHIP_FIJI) || in gmc_v8_0_sw_init() 1107 (adev->asic_type == CHIP_VEGAM)) in gmc_v8_0_sw_init() 1238 if (adev->asic_type == CHIP_TONGA) { in gmc_v8_0_hw_init() 1244 } else if (adev->asic_type == CHIP_POLARIS11 || in gmc_v8_0_hw_init() 1245 adev->asic_type == CHIP_POLARIS10 || in gmc_v8_0_hw_init() 1246 adev->asic_type == CHIP_POLARIS12) { in gmc_v8_0_hw_init() 1687 switch (adev->asic_type) { in gmc_v8_0_set_clockgating_state()
|
H A D | vi.c | 282 switch (adev->asic_type) { in vi_init_golden_registers() 454 if (adev->asic_type == CHIP_TONGA || in vi_detect_hw_virtualization() 455 adev->asic_type == CHIP_FIJI) { in vi_detect_hw_virtualization() 927 switch (adev->asic_type) { in vi_need_full_reset() 989 switch (adev->asic_type) { in vi_common_early_init() 1491 switch (adev->asic_type) { in vi_common_set_clockgating_state() 1595 switch (adev->asic_type) { in vi_set_ip_blocks()
|
H A D | dce_v11_0.c | 157 switch (adev->asic_type) { in dce_v11_0_init_golden_registers() 471 switch (adev->asic_type) { in dce_v11_0_get_num_crtc() 1446 switch (adev->asic_type) { in dce_v11_0_audio_init() 2253 if ((adev->asic_type == CHIP_POLARIS10) || in dce_v11_0_pick_pll() 2254 (adev->asic_type == CHIP_POLARIS11) || in dce_v11_0_pick_pll() 2255 (adev->asic_type == CHIP_POLARIS12) || in dce_v11_0_pick_pll() 2256 (adev->asic_type == CHIP_VEGAM)) { in dce_v11_0_pick_pll() 2308 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) { in dce_v11_0_pick_pll() 2676 (adev->asic_type == CHIP_VEGAM)) { in dce_v11_0_crtc_mode_set() 2823 switch (adev->asic_type) { in dce_v11_0_early_init() [all …]
|
H A D | amdgpu_display.c | 498 if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type < CHIP_RAVEN && in amdgpu_display_supported_domains() 500 amdgpu_device_asic_has_dc_support(adev->asic_type)) in amdgpu_display_supported_domains()
|
H A D | atombios_crtc.c | 501 if (adev->asic_type == CHIP_TAHITI || in amdgpu_atombios_crtc_set_disp_eng_pll() 502 adev->asic_type == CHIP_PITCAIRN || in amdgpu_atombios_crtc_set_disp_eng_pll() 503 adev->asic_type == CHIP_VERDE || in amdgpu_atombios_crtc_set_disp_eng_pll() 504 adev->asic_type == CHIP_OLAND) in amdgpu_atombios_crtc_set_disp_eng_pll()
|
H A D | sdma_v4_0.c | 156 switch (adev->asic_type) { in sdma_v4_0_init_golden_registers() 214 switch (adev->asic_type) { in sdma_v4_0_init_microcode() 805 switch (adev->asic_type) { in sdma_v4_0_init_pg() 1214 if (adev->asic_type == CHIP_RAVEN) in sdma_v4_0_early_init() 1552 switch (adev->asic_type) { in sdma_v4_0_set_clockgating_state() 1573 switch (adev->asic_type) { in sdma_v4_0_set_powergating_state()
|
H A D | amdgpu_kms.c | 704 if (adev->asic_type < CHIP_POLARIS10) { in amdgpu_info_ioctl() 941 if (adev->asic_type != CHIP_RAVEN) { in amdgpu_driver_postclose_kms() 1208 if (adev->asic_type == CHIP_KAVERI || in amdgpu_debugfs_firmware_info() 1209 (adev->asic_type > CHIP_TOPAZ && adev->asic_type != CHIP_STONEY)) { in amdgpu_debugfs_firmware_info()
|
H A D | amdgpu_amdkfd.c | 91 switch (adev->asic_type) { in amdgpu_amdkfd_device_probe() 192 if (adev->asic_type >= CHIP_VEGA10) { in amdgpu_amdkfd_device_init()
|
H A D | amdgpu_cgs.c | 141 if (adev->asic_type >= CHIP_TOPAZ) in fw_type_convert() 250 switch (adev->asic_type) { in amdgpu_cgs_get_firmware_info()
|
H A D | cik.c | 755 switch (adev->asic_type) { in cik_init_golden_registers() 1777 switch (adev->asic_type) { in cik_common_early_init() 1881 if (adev->asic_type == CHIP_KABINI) { in cik_common_early_init() 2000 switch (adev->asic_type) { in cik_set_ip_blocks()
|
H A D | gmc_v7_0.c | 72 switch (adev->asic_type) { in gmc_v7_0_init_golden_registers() 136 switch (adev->asic_type) { in gmc_v7_0_init_microcode() 393 switch (adev->asic_type) { in gmc_v7_0_mc_init() 690 if (adev->asic_type == CHIP_KAVERI) { in gmc_v7_0_gart_enable()
|
H A D | dce_virtual.c | 433 switch (adev->asic_type) { in dce_virtual_hw_init() 473 DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type); in dce_virtual_hw_init()
|
H A D | vce_v4_0.c | 887 if ((adev->asic_type == CHIP_POLARIS10) || 888 (adev->asic_type == CHIP_TONGA) || 889 (adev->asic_type == CHIP_FIJI))
|
H A D | sdma_v3_0.c | 197 switch (adev->asic_type) { in sdma_v3_0_init_golden_registers() 276 switch (adev->asic_type) { in sdma_v3_0_init_microcode() 1156 switch (adev->asic_type) { in sdma_v3_0_early_init() 1564 switch (adev->asic_type) { in sdma_v3_0_set_clockgating_state()
|
H A D | gfx_v9_0.c | 257 switch (adev->asic_type) { in gfx_v9_0_init_golden_registers() 502 switch (adev->asic_type) { in gfx_v9_0_init_microcode() 967 if (adev->asic_type == CHIP_RAVEN) { in gfx_v9_0_rlc_init() 1176 switch (adev->asic_type) { in gfx_v9_0_gpu_early_init() 1489 switch (adev->asic_type) { in gfx_v9_0_sw_init() 1655 if (adev->asic_type == CHIP_RAVEN) { in gfx_v9_0_sw_fini() 2190 if (adev->asic_type == CHIP_VEGA12) in gfx_v9_0_init_pg() 2305 if (adev->asic_type == CHIP_RAVEN) { in gfx_v9_0_rlc_resume() 3749 switch (adev->asic_type) { in gfx_v9_0_set_powergating_state() 3794 switch (adev->asic_type) { in gfx_v9_0_set_clockgating_state() [all …]
|
/dragonfly/sys/dev/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm.c | 443 adev->asic_type >= CHIP_CARRIZO && in amdgpu_dm_init() 444 adev->asic_type < CHIP_RAVEN) in amdgpu_dm_init() 1255 if (adev->asic_type == CHIP_VEGA10 || in dce110_register_irq_handlers() 1256 adev->asic_type == CHIP_VEGA12 || in dce110_register_irq_handlers() 1257 adev->asic_type == CHIP_VEGA20 || in dce110_register_irq_handlers() 1258 adev->asic_type == CHIP_RAVEN) in dce110_register_irq_handlers() 1662 switch (adev->asic_type) { in amdgpu_dm_initialize_drm_device() 1697 if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY) in amdgpu_dm_initialize_drm_device() 1806 switch (adev->asic_type) { in dm_early_init() 2109 if (adev->asic_type == CHIP_VEGA10 || in fill_plane_attributes_from_fb() [all …]
|