Searched refs:cfgcr0 (Results 1 – 4 of 4) sorted by relevance
1991 val = pll->state.hw_state.cfgcr0; in cnl_ddi_pll_enable()2115 hw_state->cfgcr0 = val; in cnl_ddi_pll_get_hw_state()2269 uint32_t cfgcr0, cfgcr1; in cnl_ddi_hdmi_pll_dividers() local2272 cfgcr0 = DPLL_CFGCR0_HDMI_MODE; in cnl_ddi_hdmi_pll_dividers()2290 crtc_state->dpll_hw_state.cfgcr0 = cfgcr0; in cnl_ddi_hdmi_pll_dividers()2299 uint32_t cfgcr0; in cnl_ddi_dp_set_dpll_hw_state() local2301 cfgcr0 = DPLL_CFGCR0_SSC_ENABLE; in cnl_ddi_dp_set_dpll_hw_state()2305 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_810; in cnl_ddi_dp_set_dpll_hw_state()2308 cfgcr0 |= DPLL_CFGCR0_LINK_RATE_1350; in cnl_ddi_dp_set_dpll_hw_state()2333 dpll_hw_state->cfgcr0 = cfgcr0; in cnl_ddi_dp_set_dpll_hw_state()[all …]
132 uint32_t cfgcr0; member
1221 uint32_t cfgcr0, cfgcr1; in cnl_calc_wrpll_link() local1224 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); in cnl_calc_wrpll_link()1266 dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock; in cnl_calc_wrpll_link()1268 dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> in cnl_calc_wrpll_link()1306 uint32_t cfgcr0; in cnl_ddi_clock_get() local1311 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); in cnl_ddi_clock_get()1313 if (cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { in cnl_ddi_clock_get()1316 link_clock = cfgcr0 & DPLL_CFGCR0_LINK_RATE_MASK; in cnl_ddi_clock_get()
11295 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); in intel_pipe_config_compare()