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Searched refs:cfgcr1 (Results 1 – 4 of 4) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_dpll_mgr.c888 i915_reg_t ctl, cfgcr1, cfgcr2; member
901 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
907 .cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
940 I915_WRITE(regs[pll->id].cfgcr1, pll->state.hw_state.cfgcr1); in skl_ddi_pll_enable()
1001 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); in skl_ddi_pll_get_hw_state()
1291 uint32_t ctrl1, cfgcr1, cfgcr2; in skl_ddi_hdmi_pll_dividers() local
1319 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; in skl_ddi_hdmi_pll_dividers()
1413 hw_state->cfgcr1, in skl_dump_hw_state()
2269 uint32_t cfgcr0, cfgcr1; in cnl_ddi_hdmi_pll_dividers() local
2291 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; in cnl_ddi_hdmi_pll_dividers()
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H A Dintel_dpll_mgr.h129 uint32_t cfgcr1, cfgcr2; member
H A Dintel_ddi.c1221 uint32_t cfgcr0, cfgcr1; in cnl_calc_wrpll_link() local
1225 cfgcr1 = I915_READ(CNL_DPLL_CFGCR1(pll_id)); in cnl_calc_wrpll_link()
1227 p0 = cfgcr1 & DPLL_CFGCR1_PDIV_MASK; in cnl_calc_wrpll_link()
1228 p2 = cfgcr1 & DPLL_CFGCR1_KDIV_MASK; in cnl_calc_wrpll_link()
1230 if (cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1)) in cnl_calc_wrpll_link()
1231 p1 = (cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >> in cnl_calc_wrpll_link()
H A Dintel_display.c11293 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); in intel_pipe_config_compare()