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Searched refs:clk (Results 1 – 25 of 61) sorted by relevance

123

/dragonfly/sys/dev/drm/amd/display/dc/dce/
H A Ddce_clocks.c53 clk->ctx->logger
177 struct dce_dccg *clk_dce = TO_DCE_CLOCKS(clk); in dce_get_dp_ref_freq_khz()
209 struct dccg *clk, in dce_get_required_clocks_state() argument
228 if (low_req_clk > clk->max_clks_state) { in dce_get_required_clocks_state()
234 low_req_clk = clk->max_clks_state; in dce_get_required_clocks_state()
241 struct dccg *clk, in dce_set_clock() argument
246 struct dc_bios *bp = clk->ctx->dc_bios; in dce_set_clock()
276 struct dccg *clk, in dce_psr_set_clock() argument
292 struct dccg *clk, in dce112_set_clock() argument
297 struct dc_bios *bp = clk->ctx->dc_bios; in dce112_set_clock()
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/dragonfly/sys/dev/drm/amd/display/dc/core/
H A Ddc_debug.c355 context->bw.dcn.clk.dispclk_khz, in context_clock_trace()
356 context->bw.dcn.clk.dppclk_khz, in context_clock_trace()
357 context->bw.dcn.clk.dcfclk_khz, in context_clock_trace()
358 context->bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
359 context->bw.dcn.clk.fclk_khz, in context_clock_trace()
360 context->bw.dcn.clk.socclk_khz); in context_clock_trace()
363 context->bw.dcn.clk.dispclk_khz, in context_clock_trace()
364 context->bw.dcn.clk.dppclk_khz, in context_clock_trace()
365 context->bw.dcn.clk.dcfclk_khz, in context_clock_trace()
367 context->bw.dcn.clk.fclk_khz, in context_clock_trace()
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/dragonfly/sys/dev/drm/amd/display/dc/bios/
H A Dcommand_table.c1022 memset(&clk, 0, sizeof(clk)); in set_pixel_clock_v5()
1029 clk.sPCLKInput.ucRefDiv = in set_pixel_clock_v5()
1031 clk.sPCLKInput.usFbDiv = in set_pixel_clock_v5()
1035 clk.sPCLKInput.ucPostDiv = in set_pixel_clock_v5()
1046 clk.sPCLKInput.usPixelClock = in set_pixel_clock_v5()
1079 memset(&clk, 0, sizeof(clk)); in set_pixel_clock_v6()
1105 clk.sPCLKInput.ucRefDiv = in set_pixel_clock_v6()
1107 clk.sPCLKInput.usFbDiv = in set_pixel_clock_v6()
1111 clk.sPCLKInput.ucPostDiv = in set_pixel_clock_v6()
1157 memset(&clk, 0, sizeof(clk)); in set_pixel_clock_v7()
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H A Dcommand_table2.c265 struct set_pixel_clock_parameter_v1_7 clk; in set_pixel_clock_v7() local
269 memset(&clk, 0, sizeof(clk)); in set_pixel_clock_v7()
293 clk.crtc_id = controller_id; in set_pixel_clock_v7()
294 clk.pll_id = (uint8_t) pll_id; in set_pixel_clock_v7()
295 clk.encoderobjid = in set_pixel_clock_v7()
300 clk.encoder_mode = (uint8_t) bp-> in set_pixel_clock_v7()
308 clk.deep_color_ratio = in set_pixel_clock_v7()
317 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL; in set_pixel_clock_v7()
320 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_PROG_PHYPLL; in set_pixel_clock_v7()
323 clk.miscinfo |= PIXEL_CLOCK_V7_MISC_YUV420_MODE; in set_pixel_clock_v7()
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/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dsmu10_hwmgr.c155 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0; in smu10_init_dynamic_state_adjustment_rule_settings()
157 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1; in smu10_init_dynamic_state_adjustment_rule_settings()
159 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2; in smu10_init_dynamic_state_adjustment_rule_settings()
835 mclk_table->entries[low].clk/100); in smu10_force_clock_level()
839 mclk_table->entries[high].clk/100); in smu10_force_clock_level()
887 mclk_table->entries[i].clk / 100, in smu10_print_clock_levels()
888 ((mclk_table->entries[i].clk / 100) in smu10_print_clock_levels()
997 if (pclk_vol_table->entries[i].clk) { in smu10_get_clock_by_type_with_latency()
999 pclk_vol_table->entries[i].clk * 10; in smu10_get_clock_by_type_with_latency()
1002 pclk_vol_table->entries[i].clk) : in smu10_get_clock_by_type_with_latency()
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H A Dsmu8_hwmgr.c110 if (clock <= table->entries[i].clk) in smu8_get_sclk_level()
118 if (clock >= table->entries[i].clk) in smu8_get_sclk_level()
570 clock = table->entries[level].clk; in smu8_init_sclk_limit()
572 clock = table->entries[table->count - 1].clk; in smu8_init_sclk_limit()
1149 hwmgr->pstate_sclk = table->entries[0].clk; in smu8_phm_unforce_dpm_levels()
1155 clock = table->entries[level].clk; in smu8_phm_unforce_dpm_levels()
1157 clock = table->entries[table->count - 1].clk; in smu8_phm_unforce_dpm_levels()
1482 info->level = table->entries[i].clk; in smu8_get_dal_power_level()
1526 i, sclk_table->entries[i].clk / 100, in smu8_print_clock_levels()
1613 clocks->clock[i] = table->entries[i].clk * 10; in smu8_get_clock_by_type()
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H A Dvega10_hwmgr.c332 od_table[2]->entries[i].clk; in vega10_odn_initial_default_setting()
1209 dep_table->entries[i].clk) { in vega10_setup_default_single_dpm_table()
1211 dep_table->entries[i].clk; in vega10_setup_default_single_dpm_table()
1830 uint16_t clk = 0, vddc = 0; in vega10_populate_single_display_type() local
1855 clk = (uint16_t)(dep_table->entries[i].clk / 100); in vega10_populate_single_display_type()
1860 cpu_to_le16(clk); in vega10_populate_single_display_type()
1867 cpu_to_le16(clk); in vega10_populate_single_display_type()
4119 dep_table->entries[i].clk; in vega10_get_memclocks()
4714 uint32_t clk, in vega10_check_clk_voltage_valid() argument
4788 dep_table->entries[i].clk < podn_vdd_dep->entries[dep_table->count-1].clk) { in vega10_odn_update_soc_table()
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H A Dsmu_helper.c435 *sclk = table_info->vdd_dep_on_sclk->entries[entry_id].clk; in phm_get_sclk_for_voltage_evv()
460 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_ULTRALOW; in phm_initializa_dynamic_state_adjustment_rule_settings()
462 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_LOW; in phm_initializa_dynamic_state_adjustment_rule_settings()
464 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_NOMINAL; in phm_initializa_dynamic_state_adjustment_rule_settings()
466 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_PERFORMANCE; in phm_initializa_dynamic_state_adjustment_rule_settings()
502 if (dal_power_level == table->entries[i].clk) { in phm_apply_dal_min_voltage_request()
642 dep_table->entries[i].clk = allowed_dep_table->entries[i].clk; in smu_get_voltage_dependency_table_ppt_v1()
H A Dsmu7_hwmgr.c695 allowed_vdd_sclk_table->entries[i].clk; in smu7_setup_dpm_tables_v0()
786 dep_sclk_table->entries[i].clk) { in smu7_setup_dpm_tables_v1()
789 dep_sclk_table->entries[i].clk; in smu7_setup_dpm_tables_v1()
803 dep_mclk_table->entries[i].clk) { in smu7_setup_dpm_tables_v1()
805 dep_mclk_table->entries[i].clk; in smu7_setup_dpm_tables_v1()
3239 if (dep_mclk_table->entries[0].clk != in smu7_get_pp_table_entry_v1()
3387 if (dep_mclk_table->entries[0].clk != in smu7_get_pp_table_entry_v0()
4666 if (clk >= MEM_FREQ_LOW_LATENCY && clk < MEM_FREQ_HIGH_LATENCY) in smu7_get_mem_latency()
4668 else if (clk >= MEM_FREQ_HIGH_LATENCY) in smu7_get_mem_latency()
4689 dep_mclk_table->entries[i].clk); in smu7_get_mclks()
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H A Dvega10_processpptables.c545 clk_table->entries[i].clk = in get_socclk_voltage_dependency_table()
583 mclk_table->entries[i].clk = in get_mclk_voltage_dependency_table()
621 clk_table->entries[i].clk = in get_gfxclk_voltage_dependency_table()
636 clk_table->entries[i].clk = in get_gfxclk_voltage_dependency_table()
686 clk_table->entries[i].clk = in get_pix_clk_voltage_dependency_table()
743 clk_table->entries[i].clk = in get_dcefclk_voltage_dependency_table()
749 clk_table->entries[i].clk = 90000; in get_dcefclk_voltage_dependency_table()
846 table->values[i] = (uint32_t)clk_volt_pp_table->entries[i].clk; in get_valid_clk()
H A Dhwmgr_ppt.h32 uint32_t clk; member
/dragonfly/sbin/routed/
H A Dmain.c58 struct timeval clk, prev_clk; variable
108 gettimeofday(&clk, 0); in main()
109 prev_clk = clk; in main()
110 epoch = clk; in main()
275 srandom((int)(clk.tv_sec ^ clk.tv_usec ^ mypid)); in main()
334 prev_clk = clk; in main()
335 gettimeofday(&clk, 0); in main()
336 if (prev_clk.tv_sec == clk.tv_sec in main()
344 clk.tv_usec += ++usec_fudge; in main()
349 timevalsub(&t2, &clk, &prev_clk); in main()
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/dragonfly/contrib/nvi2/common/
H A Dutil.c340 clock_serv_t clk; local
344 kr = host_get_clock_service(mach_host_self(), CALENDAR_CLOCK, &clk);
347 (void)clock_get_time(clk, &mts);
348 (void)mach_port_deallocate(mach_task_self(), clk);
/dragonfly/sys/dev/drm/radeon/
H A Dkv_dpm.c720 if (table->entries[i].clk == pi->boot_pl.sclk) in kv_program_bootup_state()
795 if (kv_get_clock_difference(clk, 40000) < 200) in kv_get_clk_bypass()
797 else if (kv_get_clock_difference(clk, 30000) < 200) in kv_get_clk_bypass()
799 else if (kv_get_clock_difference(clk, 20000) < 200) in kv_get_clk_bypass()
801 else if (kv_get_clock_difference(clk, 15000) < 200) in kv_get_clk_bypass()
973 table->entries[i].clk, false, &dividers); in kv_populate_samu_table()
1032 table->entries[i].clk, false, &dividers); in kv_populate_acp_table()
1551 if (table->entries[i].clk >= 0) /* XXX */ in kv_get_acp_boot_level()
2166 stable_p_state_sclk = table->entries[i].clk; in kv_apply_state_adjust_rules()
2172 stable_p_state_sclk = table->entries[0].clk; in kv_apply_state_adjust_rules()
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H A Dci_smc.c157 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in ci_is_smc_running() local
160 if (!(clk & CK_DISABLE) && (0x20100 <= pc_c)) in ci_is_smc_running()
H A Dsi_smc.c164 u32 clk = RREG32_SMC(SMC_SYSCON_CLOCK_CNTL_0); in si_is_smc_running() local
166 if (!(rst & RST_REG) && !(clk & CK_DISABLE)) in si_is_smc_running()
/dragonfly/sys/bus/u4b/serial/
H A Dumcs.c664 uint8_t clk; in umcs7840_pre_param() local
667 if (umcs7840_calc_baudrate(t->c_ospeed, &divisor, &clk) || !divisor) in umcs7840_pre_param()
1008 uint8_t clk; in umcs7840_set_baudrate() local
1011 if (umcs7840_calc_baudrate(rate, &divisor, &clk)) { in umcs7840_set_baudrate()
1015 if (divisor == 0 || (clk & MCS7840_DEV_SPx_CLOCK_MASK) != clk) { in umcs7840_set_baudrate()
1019 DPRINTF("Port %d set speed: %d (%02x / %d)\n", portno, rate, clk, divisor); in umcs7840_set_baudrate()
1026 data |= clk; in umcs7840_set_baudrate()
1057 umcs7840_calc_baudrate(uint32_t rate, uint16_t *divisor, uint8_t *clk) in umcs7840_calc_baudrate() argument
1068 *clk = i << MCS7840_DEV_SPx_CLOCK_SHIFT; in umcs7840_calc_baudrate()
/dragonfly/sys/dev/drm/amd/display/dc/dce120/
H A Ddce120_resource.c738 unsigned int clk; in bw_calcs_data_update_from_pplib() local
748 clk = 300000; in bw_calcs_data_update_from_pplib()
751 eng_clks.data[i].clocks_in_khz = clk; in bw_calcs_data_update_from_pplib()
752 clk += 100000; in bw_calcs_data_update_from_pplib()
781 clk = 250000; in bw_calcs_data_update_from_pplib()
785 mem_clks.data[i].clocks_in_khz = clk; in bw_calcs_data_update_from_pplib()
787 clk += 500000; in bw_calcs_data_update_from_pplib()
/dragonfly/sys/dev/drm/amd/display/dc/calcs/
H A Ddcn_calcs.c1042 context->bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / in dcn_validate_bandwidth()
1045 context->bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32); in dcn_validate_bandwidth()
1049 context->bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000); in dcn_validate_bandwidth()
1051 context->bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000); in dcn_validate_bandwidth()
1055 if (context->bw.dcn.clk.dispclk_khz < in dcn_validate_bandwidth()
1057 context->bw.dcn.clk.dispclk_khz = in dcn_validate_bandwidth()
1061 context->bw.dcn.clk.dppclk_khz = context->bw.dcn.clk.dispclk_khz / v->dispclk_dppclk_ratio; in dcn_validate_bandwidth()
1065 context->bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()
1069 context->bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()
1073 context->bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()
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/dragonfly/sys/dev/disk/sdhci/
H A Dsdhci.c257 uint16_t clk; in sdhci_set_clock() local
266 clk = RD2(slot, SDHCI_CLOCK_CONTROL); in sdhci_set_clock()
267 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); in sdhci_set_clock()
320 clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; in sdhci_set_clock()
321 clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) in sdhci_set_clock()
324 WR2(slot, SDHCI_CLOCK_CONTROL, clk); in sdhci_set_clock()
326 clk |= SDHCI_CLOCK_INT_EN; in sdhci_set_clock()
327 WR2(slot, SDHCI_CLOCK_CONTROL, clk); in sdhci_set_clock()
330 while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) in sdhci_set_clock()
342 clk |= SDHCI_CLOCK_CARD_EN; in sdhci_set_clock()
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/dragonfly/sys/dev/drm/
H A Ddrm_dp_helper.c548 int clk; in drm_dp_downstream_debug() local
603 clk = drm_dp_downstream_max_clock(dpcd, port_cap); in drm_dp_downstream_debug()
605 if (clk > 0) { in drm_dp_downstream_debug()
607 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk); in drm_dp_downstream_debug()
609 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk); in drm_dp_downstream_debug()
/dragonfly/sys/dev/drm/amd/powerplay/
H A Damd_powerplay.c375 uint32_t clk = 0; in pp_dpm_get_sclk() local
385 clk = hwmgr->hwmgr_func->get_sclk(hwmgr, low); in pp_dpm_get_sclk()
387 return clk; in pp_dpm_get_sclk()
393 uint32_t clk = 0; in pp_dpm_get_mclk() local
403 clk = hwmgr->hwmgr_func->get_mclk(hwmgr, low); in pp_dpm_get_mclk()
405 return clk; in pp_dpm_get_mclk()
/dragonfly/sys/dev/drm/amd/powerplay/smumgr/
H A Dpolaris10_smumgr.c367 if (dep_table->entries[i].clk >= clock) { in polaris10_get_dependency_volt_by_clk()
1183 if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) { in polaris10_populate_mvdd_value()
1490 if (table_info->vdd_dep_on_sclk->entries[level].clk >= in polaris10_populate_smc_initailial_state()
1499 if (table_info->vdd_dep_on_mclk->entries[level].clk >= in polaris10_populate_smc_initailial_state()
1558 …volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70)… in polaris10_populate_clock_stretcher_data_table()
1559 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000)); in polaris10_populate_clock_stretcher_data_table()
1560 …volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000… in polaris10_populate_clock_stretcher_data_table()
1561 (2522480 - sclk_table->entries[i].clk/100 * 115764/100)); in polaris10_populate_clock_stretcher_data_table()
1564 (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000))); in polaris10_populate_clock_stretcher_data_table()
1565 …volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 10… in polaris10_populate_clock_stretcher_data_table()
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/dragonfly/sys/dev/drm/amd/display/dc/dcn10/
H A Ddcn10_hw_sequencer.c344 dc->current_state->bw.dcn.clk.dcfclk_khz, in dcn10_log_hw_state()
345 dc->current_state->bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_log_hw_state()
346 dc->current_state->bw.dcn.clk.dispclk_khz, in dcn10_log_hw_state()
347 dc->current_state->bw.dcn.clk.dppclk_khz, in dcn10_log_hw_state()
348 dc->current_state->bw.dcn.clk.max_supported_dppclk_khz, in dcn10_log_hw_state()
349 dc->current_state->bw.dcn.clk.fclk_khz, in dcn10_log_hw_state()
350 dc->current_state->bw.dcn.clk.socclk_khz); in dcn10_log_hw_state()
2019 bool should_divided_by_2 = context->bw.dcn.clk.dppclk_khz <= in update_dchubp_dpp()
2383 context->bw.dcn.clk.phyclk_khz = 0; in dcn10_set_bandwidth()
2387 &context->bw.dcn.clk, in dcn10_set_bandwidth()
/dragonfly/sys/dev/netif/alc/
H A Dif_alc.c291 uint32_t clk, v; in alc_mii_readreg_816x() local
295 clk = MDIO_CLK_25_128; in alc_mii_readreg_816x()
297 clk = MDIO_CLK_25_4; in alc_mii_readreg_816x()
354 uint32_t clk, v; in alc_mii_writereg_816x() local
358 clk = MDIO_CLK_25_128; in alc_mii_writereg_816x()
360 clk = MDIO_CLK_25_4; in alc_mii_writereg_816x()
448 uint32_t clk, v; in alc_miiext_readreg() local
454 clk = MDIO_CLK_25_128; in alc_miiext_readreg()
456 clk = MDIO_CLK_25_4; in alc_miiext_readreg()
478 uint32_t clk, v; in alc_miiext_writereg() local
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