Searched refs:crtc_offsets (Results 1 – 7 of 7) sorted by relevance
/dragonfly/sys/dev/drm/radeon/ |
H A D | rv515.c | 42 static const u32 crtc_offsets[2] = variable 307 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop() 312 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop() 325 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop() 327 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop() 360 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_stop() 363 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); in rv515_mc_stop() 410 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_resume() 413 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp); in rv515_mc_resume() 421 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]); in rv515_mc_resume() [all …]
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H A D | evergreen.c | 111 static const u32 crtc_offsets[6] = variable 2705 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop() 2730 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_stop() 2733 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in evergreen_mc_stop() 4458 WREG32(INT_MASK + crtc_offsets[i], 0); in evergreen_disable_interrupt_state() 4460 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); in evergreen_disable_interrupt_state() 4558 rdev, INT_MASK + crtc_offsets[i], in evergreen_irq_set() 4581 rdev, AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i], in evergreen_irq_set() 4611 WREG32(GRPH_INT_STATUS + crtc_offsets[j], in evergreen_irq_ack() 4617 WREG32(VBLANK_STATUS + crtc_offsets[j], in evergreen_irq_ack() [all …]
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H A D | rs600.c | 49 static const u32 crtc_offsets[2] = variable 57 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) in avivo_is_in_vblank() 67 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving() 68 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving() 91 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()
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H A D | si.c | 132 static const u32 crtc_offsets[] = variable 5951 WREG32(INT_MASK + crtc_offsets[i], 0); in si_disable_interrupt_state() 5953 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], 0); in si_disable_interrupt_state() 6105 rdev, INT_MASK + crtc_offsets[i], VBLANK_INT_MASK, in si_irq_set() 6111 WREG32(GRPH_INT_CONTROL + crtc_offsets[i], GRPH_PFLIP_INT_MASK); in si_irq_set() 6143 grph_int[i] = RREG32(GRPH_INT_STATUS + crtc_offsets[i]); in si_irq_ack() 6150 WREG32(GRPH_INT_STATUS + crtc_offsets[j], in si_irq_ack() 6156 WREG32(VBLANK_STATUS + crtc_offsets[j], in si_irq_ack() 6159 WREG32(VLINE_STATUS + crtc_offsets[j], in si_irq_ack()
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H A D | r600.c | 94 static const u32 crtc_offsets[2] = variable 1584 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { in r600_is_display_hung() 1585 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung() 1593 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
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/dragonfly/sys/dev/drm/amd/amdgpu/ |
H A D | dce_v10_0.c | 49 static const u32 crtc_offsets[] = variable 406 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_is_display_hung() 480 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v10_0_disable_dce() 481 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_disable_dce() 483 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v10_0_disable_dce() 484 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v10_0_disable_dce() 3083 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v10_0_set_pageflip_irq_state() 3086 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v10_0_set_pageflip_irq_state() 3172 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); in dce_v10_0_crtc_vblank_int_ack() 3185 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); in dce_v10_0_crtc_vline_int_ack() [all …]
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H A D | dce_v11_0.c | 49 static const u32 crtc_offsets[] = variable 422 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_is_display_hung() 506 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); in dce_v11_0_disable_dce() 507 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_disable_dce() 509 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v11_0_disable_dce() 510 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); in dce_v11_0_disable_dce() 3209 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v11_0_set_pageflip_irq_state() 3212 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type], in dce_v11_0_set_pageflip_irq_state() 3298 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); in dce_v11_0_crtc_vblank_int_ack() 3311 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); in dce_v11_0_crtc_vline_int_ack() [all …]
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