Searched refs:current_sclk (Results 1 – 19 of 19) sorted by relevance
205 if (sclk < rdev->pm.current_sclk) in radeon_set_power_state()222 if (sclk != rdev->pm.current_sclk) { in radeon_set_power_state()226 rdev->pm.current_sclk = sclk; in radeon_set_power_state()1297 rdev->pm.current_sclk = rdev->pm.default_sclk; in radeon_pm_resume_old()1367 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_pm_init_old()1433 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_pm_init_dpm()1978 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); in radeon_debugfs_pm_info()
1410 u32 current_sclk; in trinity_patch_thermal_state() local1415 current_sclk = current_ps->levels[current_index].sclk; in trinity_patch_thermal_state()1418 current_sclk = pi->boot_pl.sclk; in trinity_patch_thermal_state()1423 if (ps->levels[0].sclk > current_sclk) in trinity_patch_thermal_state()1424 ps->levels[0].sclk = current_sclk; in trinity_patch_thermal_state()
1052 u32 current_sclk; in sumo_patch_thermal_state() local1057 current_sclk = current_ps->levels[current_index].sclk; in sumo_patch_thermal_state()1060 current_sclk = pi->boot_pl.sclk; in sumo_patch_thermal_state()1065 if (ps->levels[0].sclk > current_sclk) in sumo_patch_thermal_state()1066 ps->levels[0].sclk = current_sclk; in sumo_patch_thermal_state()
341 rdev->pm.current_sclk = rdev->clock.default_sclk; in radeon_get_clock_info()
614 *value = rdev->pm.current_sclk / 100; in radeon_info_ioctl()
238 u32 sclk = rdev->pm.current_sclk; in radeon_get_i2c_prescale()
293 selected_sclk = rdev->pm.current_sclk; in rs690_crtc_bandwidth_compute()
750 u32 sclk = rdev->pm.current_sclk; in radeon_update_bandwidth_info()
972 selected_sclk = rdev->pm.current_sclk; in rv515_crtc_bandwidth_compute()
2169 wm_high.sclk = rdev->pm.current_sclk * 10; in evergreen_program_watermarks()2196 wm_low.sclk = rdev->pm.current_sclk * 10; in evergreen_program_watermarks()
2322 wm_high.sclk = rdev->pm.current_sclk * 10; in dce6_program_watermarks()2349 wm_low.sclk = rdev->pm.current_sclk * 10; in dce6_program_watermarks()
1630 u32 current_sclk; member
9242 wm_high.sclk = rdev->pm.current_sclk * 10; in dce8_program_watermarks()9282 wm_low.sclk = rdev->pm.current_sclk * 10; in dce8_program_watermarks()
267 adev->pm.current_sclk = adev->clock.default_sclk; in amdgpu_atomfirmware_get_clock_info()
411 u32 current_sclk; member
1038 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()1077 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v10_0_program_watermarks()
1064 wm_high.sclk = adev->pm.current_sclk * 10; in dce_v11_0_program_watermarks()1103 wm_low.sclk = adev->pm.current_sclk * 10; in dce_v11_0_program_watermarks()
701 adev->pm.current_sclk = adev->clock.default_sclk; in amdgpu_atombios_get_clock_info()
7704 adev->pm.current_sclk = adev->clock.default_sclk; in si_dpm_sw_init()