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Searched refs:dfixed_mul (Results 1 – 9 of 9) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
H A Drs690.c334 b.full = dfixed_mul(b, crtc->hsc); in rs690_crtc_bandwidth_compute()
351 line_time.full = dfixed_mul(a, pclk); in rs690_crtc_bandwidth_compute()
386 sclk.full = dfixed_mul(max_bandwidth, a); in rs690_crtc_bandwidth_compute()
395 chunk_time.full = dfixed_mul(sclk, a); in rs690_crtc_bandwidth_compute()
486 b.full = dfixed_mul(b, wm0->active_time); in rs690_compute_mode_priority()
487 a.full = dfixed_mul(wm0->worst_case_latency, in rs690_compute_mode_priority()
493 a.full = dfixed_mul(wm0->worst_case_latency, in rs690_compute_mode_priority()
500 b.full = dfixed_mul(b, wm1->active_time); in rs690_compute_mode_priority()
501 a.full = dfixed_mul(wm1->worst_case_latency, in rs690_compute_mode_priority()
534 b.full = dfixed_mul(b, wm0->active_time); in rs690_compute_mode_priority()
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H A Drv515.c1009 b.full = dfixed_mul(b, crtc->hsc); in rv515_crtc_bandwidth_compute()
1026 line_time.full = dfixed_mul(a, pclk); in rv515_crtc_bandwidth_compute()
1132 b.full = dfixed_mul(b, wm0->active_time); in rv515_compute_mode_priority()
1135 a.full = dfixed_mul(wm0->worst_case_latency, in rv515_compute_mode_priority()
1139 a.full = dfixed_mul(wm0->worst_case_latency, in rv515_compute_mode_priority()
1146 b.full = dfixed_mul(b, wm1->active_time); in rv515_compute_mode_priority()
1149 a.full = dfixed_mul(wm1->worst_case_latency, in rv515_compute_mode_priority()
1153 a.full = dfixed_mul(wm1->worst_case_latency, in rv515_compute_mode_priority()
1180 b.full = dfixed_mul(b, wm0->active_time); in rv515_compute_mode_priority()
1183 a.full = dfixed_mul(wm0->worst_case_latency, in rv515_compute_mode_priority()
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H A Devergreen.c1943 bandwidth.full = dfixed_mul(dram_channels, yclk); in evergreen_dram_bandwidth()
1944 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); in evergreen_dram_bandwidth()
1963 bandwidth.full = dfixed_mul(dram_channels, yclk); in evergreen_dram_bandwidth_for_display()
1983 bandwidth.full = dfixed_mul(a, sclk); in evergreen_data_return_bandwidth()
2003 bandwidth.full = dfixed_mul(a, disp_clk); in evergreen_dmif_request_bandwidth()
2036 bandwidth.full = dfixed_mul(src_width, bpp); in evergreen_average_bandwidth()
2037 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in evergreen_average_bandwidth()
2241 c.full = dfixed_mul(c, b); in evergreen_program_watermarks()
2242 c.full = dfixed_mul(c, radeon_crtc->hsc); in evergreen_program_watermarks()
2253 c.full = dfixed_mul(c, b); in evergreen_program_watermarks()
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H A Dr100.c3276 mem_bw.full = dfixed_mul(mclk_ff, temp_ff); in r100_bandwidth_update()
3286 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff); in r100_bandwidth_update()
3293 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff); in r100_bandwidth_update()
3296 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff); in r100_bandwidth_update()
3397 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff); in r100_bandwidth_update()
3434 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff); in r100_bandwidth_update()
3436 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff); in r100_bandwidth_update()
3438 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff); in r100_bandwidth_update()
3439 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff); in r100_bandwidth_update()
3494 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency); in r100_bandwidth_update()
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H A Dsi.c2073 bandwidth.full = dfixed_mul(dram_channels, yclk); in dce6_dram_bandwidth()
2093 bandwidth.full = dfixed_mul(dram_channels, yclk); in dce6_dram_bandwidth_for_display()
2113 bandwidth.full = dfixed_mul(a, sclk); in dce6_data_return_bandwidth()
2136 b1.full = dfixed_mul(a, disp_clk); in dce6_dmif_request_bandwidth()
2142 b2.full = dfixed_mul(a, sclk); in dce6_dmif_request_bandwidth()
2183 bandwidth.full = dfixed_mul(src_width, bpp); in dce6_average_bandwidth()
2184 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce6_average_bandwidth()
2396 c.full = dfixed_mul(c, b); in dce6_program_watermarks()
2397 c.full = dfixed_mul(c, radeon_crtc->hsc); in dce6_program_watermarks()
2408 c.full = dfixed_mul(c, b); in dce6_program_watermarks()
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H A Dcik.c8923 bandwidth.full = dfixed_mul(dram_channels, yclk); in dce8_dram_bandwidth()
8924 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); in dce8_dram_bandwidth()
8952 bandwidth.full = dfixed_mul(dram_channels, yclk); in dce8_dram_bandwidth_for_display()
8953 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); in dce8_dram_bandwidth_for_display()
8981 bandwidth.full = dfixed_mul(a, sclk); in dce8_data_return_bandwidth()
8982 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); in dce8_data_return_bandwidth()
9007 b.full = dfixed_mul(a, disp_clk); in dce8_dmif_request_bandwidth()
9013 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); in dce8_dmif_request_bandwidth()
9063 bandwidth.full = dfixed_mul(src_width, bpp); in dce8_average_bandwidth()
9064 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce8_average_bandwidth()
/dragonfly/sys/dev/drm/include/drm/
H A Ddrm_fixed.h39 #define dfixed_mul(A, B) ((u64)((u64)(A).full * (B).full + 2048) >> 12) macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c720 bandwidth.full = dfixed_mul(dram_channels, yclk); in dce_v10_0_dram_bandwidth()
721 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); in dce_v10_0_dram_bandwidth()
749 bandwidth.full = dfixed_mul(dram_channels, yclk); in dce_v10_0_dram_bandwidth_for_display()
750 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); in dce_v10_0_dram_bandwidth_for_display()
778 bandwidth.full = dfixed_mul(a, sclk); in dce_v10_0_data_return_bandwidth()
779 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); in dce_v10_0_data_return_bandwidth()
804 b.full = dfixed_mul(a, disp_clk); in dce_v10_0_dmif_request_bandwidth()
810 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); in dce_v10_0_dmif_request_bandwidth()
860 bandwidth.full = dfixed_mul(src_width, bpp); in dce_v10_0_average_bandwidth()
861 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v10_0_average_bandwidth()
H A Ddce_v11_0.c746 bandwidth.full = dfixed_mul(dram_channels, yclk); in dce_v11_0_dram_bandwidth()
747 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); in dce_v11_0_dram_bandwidth()
775 bandwidth.full = dfixed_mul(dram_channels, yclk); in dce_v11_0_dram_bandwidth_for_display()
776 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); in dce_v11_0_dram_bandwidth_for_display()
804 bandwidth.full = dfixed_mul(a, sclk); in dce_v11_0_data_return_bandwidth()
805 bandwidth.full = dfixed_mul(bandwidth, return_efficiency); in dce_v11_0_data_return_bandwidth()
830 b.full = dfixed_mul(a, disp_clk); in dce_v11_0_dmif_request_bandwidth()
836 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); in dce_v11_0_dmif_request_bandwidth()
886 bandwidth.full = dfixed_mul(src_width, bpp); in dce_v11_0_average_bandwidth()
887 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v11_0_average_bandwidth()