Searched refs:display_config (Results 1 – 15 of 15) sorted by relevance
279 const struct amd_pp_display_configuration *display_config) in phm_store_dal_configuration_data() argument286 if (display_config == NULL) in phm_store_dal_configuration_data()290 hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk); in phm_store_dal_configuration_data()292 for (index = 0; index < display_config->num_path_including_non_display; index++) { in phm_store_dal_configuration_data()293 if (display_config->displays[index].controller_id != 0) in phm_store_dal_configuration_data()307 display_config->cpu_pstate_separation_time, in phm_store_dal_configuration_data()308 display_config->cpu_cc6_disable, in phm_store_dal_configuration_data()309 display_config->cpu_pstate_disable, in phm_store_dal_configuration_data()310 display_config->nb_pstate_switch_disable); in phm_store_dal_configuration_data()
1393 if ((hwmgr->display_config->num_display > 1) && in vega12_notify_smc_display_config_after_ps_adjustment()1394 !hwmgr->display_config->multi_monitor_in_sync && in vega12_notify_smc_display_config_after_ps_adjustment()1395 !hwmgr->display_config->nb_pstate_switch_disable) in vega12_notify_smc_display_config_after_ps_adjustment()1400 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()1401 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()1402 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()1909 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) && in vega12_apply_clocks_adjust_rules()1910 !hwmgr->display_config->multi_monitor_in_sync) || in vega12_apply_clocks_adjust_rules()1912 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega12_apply_clocks_adjust_rules()1979 if (hwmgr->display_config->nb_pstate_switch_disable) in vega12_apply_clocks_adjust_rules()[all …]
3148 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in vega10_apply_state_adjust_rules()3149 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_apply_state_adjust_rules()3189 if (hwmgr->display_config->num_display == 0) in vega10_apply_state_adjust_rules()3192 disable_mclk_switching = (hwmgr->display_config->num_display > 1) || in vega10_apply_state_adjust_rules()3224 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; in vega10_apply_state_adjust_rules()3816 if ((hwmgr->display_config->num_display > 1) && in vega10_notify_smc_display_config_after_ps_adjustment()3817 !hwmgr->display_config->multi_monitor_in_sync && in vega10_notify_smc_display_config_after_ps_adjustment()3818 !hwmgr->display_config->nb_pstate_switch_disable) in vega10_notify_smc_display_config_after_ps_adjustment()3823 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega10_notify_smc_display_config_after_ps_adjustment()3825 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_notify_smc_display_config_after_ps_adjustment()[all …]
697 clock = hwmgr->display_config->min_core_set_clock; in smu8_update_sclk_limit()752 uint32_t clks = hwmgr->display_config->min_core_set_clock_in_sr; in smu8_set_deep_sleep_sclk_threshold()1049 clocks.memoryClock = hwmgr->display_config->min_mem_set_clock != 0 ? in smu8_apply_state_adjust_rules()1050 hwmgr->display_config->min_mem_set_clock : in smu8_apply_state_adjust_rules()1058 || (hwmgr->display_config->num_display >= 3); in smu8_apply_state_adjust_rules()
2925 minimum_clocks.engineClock = hwmgr->display_config->min_core_set_clock; in smu7_apply_state_adjust_rules()2926 minimum_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in smu7_apply_state_adjust_rules()2957 if (hwmgr->display_config->num_display == 0) in smu7_apply_state_adjust_rules()2960 disable_mclk_switching = ((1 < hwmgr->display_config->num_display) || in smu7_apply_state_adjust_rules()2962 smu7_vblank_too_short(hwmgr, hwmgr->display_config->min_vblank_time)); in smu7_apply_state_adjust_rules()3632 if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display) in smu7_find_dpm_states_clocks_in_dpm_table()4048 if (hwmgr->display_config->num_display > 1 && in smu7_notify_smc_display_config_after_ps_adjustment()4049 !hwmgr->display_config->multi_monitor_in_sync) in smu7_notify_smc_display_config_after_ps_adjustment()4074 refresh_rate = hwmgr->display_config->vrefresh; in smu7_program_display_gap()4081 pre_vbi_time_in_us = frame_time_in_us - 200 - hwmgr->display_config->min_vblank_time; in smu7_program_display_gap()[all …]
204 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in smu10_set_clock_limit()632 hwmgr->display_config->num_display > 3 ? in smu10_dpm_force_dpm_level()
57 hwmgr->display_config = &adev->pm.pm_display_cfg; in amd_powerplay_create()970 const struct amd_pp_display_configuration *display_config) in pp_display_configuration_change() argument978 phm_store_dal_configuration_data(hwmgr, display_config); in pp_display_configuration_change()
430 const struct amd_pp_display_configuration *display_config);
756 const struct amd_pp_display_configuration *display_config; member
839 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in vegam_populate_single_graphic_level()843 hwmgr->display_config->min_core_set_clock_in_sr); in vegam_populate_single_graphic_level()1013 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in vegam_populate_single_memory_level()
943 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in polaris10_populate_single_graphic_level()947 hwmgr->display_config->min_core_set_clock_in_sr); in polaris10_populate_single_graphic_level()1105 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in polaris10_populate_single_memory_level()
988 data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr; in fiji_populate_single_graphic_level()992 hwmgr->display_config->min_core_set_clock_in_sr); in fiji_populate_single_graphic_level()
932 hwmgr->display_config->min_core_set_clock_in_sr; in iceland_populate_single_graphic_level()1282 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in iceland_populate_single_memory_level()
649 hwmgr->display_config->min_core_set_clock_in_sr; in tonga_populate_single_graphic_level()1006 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in tonga_populate_single_memory_level()
1234 data->display_timing.num_existing_displays = hwmgr->display_config->num_display; in ci_populate_single_memory_level()