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Searched refs:i915_ggtt_offset (Results 1 – 12 of 12) sorted by relevance

/dragonfly/sys/dev/drm/i915/
H A Dintel_lrc.c282 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE; in intel_lr_context_descriptor_update()
1119 i915_ggtt_offset(ce->ring->vma); in execlists_context_pin()
1216 *batch++ = i915_ggtt_offset(engine->scratch) + 256; in gen8_emit_flush_coherentl3_wa()
1230 *batch++ = i915_ggtt_offset(engine->scratch) + 256; in gen8_emit_flush_coherentl3_wa()
1267 i915_ggtt_offset(engine->scratch) + in gen8_init_indirectctx_bb()
1307 i915_ggtt_offset(engine->scratch) in gen9_init_indirectctx_bb()
1582 i915_ggtt_offset(ce->ring->vma); in reset_common_ring()
1729 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; in gen8_emit_flush_render()
2145 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); in execlists_init_reg_state()
2157 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); in execlists_init_reg_state()
H A Dintel_ringbuffer.c178 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; in intel_emit_post_sync_nonzero_flush()
212 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; in gen6_render_ring_flush()
282 i915_ggtt_offset(req->engine->scratch) + 2 * CACHELINE_BYTES; in gen7_render_ring_flush()
376 i915_ggtt_offset(req->engine->scratch) + in gen8_render_ring_flush()
535 I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); in init_ring_common()
561 i915_ggtt_offset(ring->vma)); in init_ring_common()
611 i915_ggtt_offset(ce->state) | in reset_ring_common()
1133 u32 *cs, cs_offset = i915_ggtt_offset(req->engine->scratch); in i830_emit_bb_start()
1924 u32 offset = i915_ggtt_offset(dev_priv->semaphore); in intel_ring_init_semaphores()
H A Dintel_guc.h100 u32 offset = i915_ggtt_offset(vma); in guc_ggtt_offset()
H A Di915_perf.c476 u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);
775 u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);
1101 i915_ggtt_offset(stream->ctx->engine[engine->id].state);
1175 u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);
1211 u32 gtt_offset = i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma);
1313 i915_ggtt_offset(dev_priv->perf.oa.oa_buffer.vma),
H A Dintel_engine_cs.c467 engine->name, i915_ggtt_offset(vma)); in intel_engine_create_scratch()
559 engine->status_page.ggtt_offset = i915_ggtt_offset(vma); in init_status_page()
563 engine->name, i915_ggtt_offset(vma)); in init_status_page()
1689 rq ? i915_ggtt_offset(rq->ring->vma) : 0); in intel_engine_dump()
H A Dintel_overlay.c853 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y); in intel_overlay_do_put_image()
867 iowrite32(i915_ggtt_offset(vma) + params->offset_U, in intel_overlay_do_put_image()
869 iowrite32(i915_ggtt_offset(vma) + params->offset_V, in intel_overlay_do_put_image()
1434 overlay->flip_addr = i915_ggtt_offset(vma); in intel_setup_overlay()
H A Dintel_fbdev.c260 info->fix.smem_start = dev->mode_config.fb_base + i915_ggtt_offset(vma); in intelfb_create()
293 fb->width, fb->height, i915_ggtt_offset(vma)); in intelfb_create()
H A Di915_vma.h195 static inline u32 i915_ggtt_offset(const struct i915_vma *vma) in i915_ggtt_offset() function
H A Di915_gem_context.c649 *cs++ = i915_ggtt_offset(req->ctx->engine[RCS].state) | flags; in mi_set_context()
675 *cs++ = i915_ggtt_offset(engine->scratch); in mi_set_context()
H A Dintel_fbc.c264 i915_ggtt_offset(params->vma) | ILK_FBC_RT_VALID); in ilk_fbc_activate()
H A Di915_gem.c1077 node.start = i915_ggtt_offset(vma); in i915_gem_gtt_pread()
1281 node.start = i915_ggtt_offset(vma); in i915_gem_gtt_pwrite_fast()
4458 i915_ggtt_offset(vma), alignment, in i915_gem_object_ggtt_pin()
H A Dintel_drv.h1491 return i915_ggtt_offset(state->vma); in intel_plane_ggtt_offset()