Searched refs:link_width (Results 1 – 7 of 7) sorted by relevance
167 int link_width; member
590 if (sc->link_width != 0 && sc->link_width <= 4) { in mxge_select_firmware()592 "expect reduced performance\n", sc->link_width); in mxge_select_firmware()1409 CTLFLAG_RD, &sc->link_width, 0, "link width"); in mxge_add_sysctls()3565 sc->link_width = (lnk >> 4) & 0x3f; in mxge_setup_cfg_space()
3461 enum pcie_link_width link_width; in amdgpu_device_get_pcie_info() local3532 link_width = pcie_get_width_cap(pdev); in amdgpu_device_get_pcie_info()3533 if (link_width == PCIE_LNK_WIDTH_UNKNOWN) { in amdgpu_device_get_pcie_info()3536 switch (link_width) { in amdgpu_device_get_pcie_info()
158 uint32_t link_width; in smu7_get_current_pcie_lane_number() local161 link_width = PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, in smu7_get_current_pcie_lane_number()164 PP_ASSERT_WITH_CODE((7 >= link_width), in smu7_get_current_pcie_lane_number()167 return decode_pcie_lane_width(link_width); in smu7_get_current_pcie_lane_number()
4856 u32 link_width = 0; in ci_get_current_pcie_lane_number() local4858 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK; in ci_get_current_pcie_lane_number()4859 link_width >>= LC_LINK_WIDTH_RD_SHIFT; in ci_get_current_pcie_lane_number()4861 switch (link_width) { in ci_get_current_pcie_lane_number()
614 kprintf("Bus (PCIe x%d, ", sc->link_width); in bce_print_adapter_info()671 sc->link_width = (link_status >> 4) & 0x3f; in bce_probe_pci_caps()
5972 uint16_t link_width; /* PCIe link width */ member