Searched refs:max_sh_per_se (Results 1 – 15 of 15) sorted by relevance
144 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()488 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
347 adev->gfx.config.max_sh_per_se = gfx_info->v24.gc_num_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
1796 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1813 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1860 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1876 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1893 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()1911 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()3587 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()3749 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()3754 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()3783 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()[all …]
431 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in get_cu_info()
1704 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()1715 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()1719 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()1722 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()1814 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()4870 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()
727 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; in amdgpu_atombios_get_gfx_info()
581 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_info_ioctl()
814 unsigned max_sh_per_se; member
1439 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se); in amdgpu_device_parse_gpu_info_fw()
492 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()494 *value = rdev->config.si.max_sh_per_se; in radeon_info_ioctl()
3093 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()3110 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()3128 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()3145 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()3162 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()3279 rdev->config.si.max_sh_per_se, in si_gpu_init()3283 rdev->config.si.max_sh_per_se, in si_gpu_init()3288 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_gpu_init()5315 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_init_ao_cu_mask()
3214 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()3231 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()3249 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()3267 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()3369 rdev->config.cik.max_sh_per_se, in cik_gpu_init()3374 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_gpu_init()5824 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_wait_for_rlc_serdes()6602 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_init_ao_cu_mask()
2143 unsigned max_sh_per_se; member2174 unsigned max_sh_per_se; member
1192 uint8_t max_sh_per_se; member1212 uint8_t max_sh_per_se; member
5653 UCHAR max_sh_per_se; member