Home
last modified time | relevance | path

Searched refs:mmAFMT_RAMP_CONTROL3 (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h385 #define mmAFMT_RAMP_CONTROL3 0x1C47 macro
H A Ddce_8_0_d.h3311 #define mmAFMT_RAMP_CONTROL3 0x1c47 macro
H A Ddce_10_0_d.h4090 #define mmAFMT_RAMP_CONTROL3 0x4a3e macro
H A Ddce_11_0_d.h3987 #define mmAFMT_RAMP_CONTROL3 0x4a3e macro
H A Ddce_11_2_d.h5218 #define mmAFMT_RAMP_CONTROL3 0x4a3e macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c1717 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); in dce_v10_0_afmt_setmode()
H A Ddce_v11_0.c1759 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); in dce_v11_0_afmt_setmode()