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Searched refs:mmDC_I2C_SW_STATUS (Results 1 – 8 of 8) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/i2caux/dce80/
H A Di2c_hw_engine_dce80.c147 value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS); in release_engine()
371 uint32_t value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS); in is_hw_busy()
383 value = dm_read_reg(engine->ctx, mmDC_I2C_SW_STATUS); in is_hw_busy()
711 uint32_t value = dm_read_reg(engine->base.ctx, mmDC_I2C_SW_STATUS); in get_channel_status()
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h1337 #define mmDC_I2C_SW_STATUS 0x181C macro
H A Ddce_8_0_d.h3545 #define mmDC_I2C_SW_STATUS 0x181c macro
H A Ddce_10_0_d.h7159 #define mmDC_I2C_SW_STATUS 0x16d7 macro
H A Ddce_11_0_d.h7348 #define mmDC_I2C_SW_STATUS 0x16d7 macro
H A Ddce_11_2_d.h8741 #define mmDC_I2C_SW_STATUS 0x16d7 macro
H A Ddce_12_0_offset.h1642 #define mmDC_I2C_SW_STATUS … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h7665 #define mmDC_I2C_SW_STATUS … macro