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Searched refs:mmDF_CS_AON0_DramBaseAddress0 (Results 1 – 3 of 3) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/df/
H A Ddf_1_7_offset.h30 #define mmDF_CS_AON0_DramBaseAddress0 0x0044 macro
/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddf_v1_7.c54 tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); in df_v1_7_get_fb_channel_number()
/dragonfly/sys/dev/drm/amd/powerplay/hwmgr/
H A Dvega10_hwmgr.c58 #define mmDF_CS_AON0_DramBaseAddress0 … macro
907 data->mem_channels = (RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0) & in vega10_hwmgr_backend_init()