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Searched refs:mmDP1_DP_DPHY_CNTL (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3169 #define mmDP1_DP_DPHY_CNTL 0x1FD0 macro
H A Ddce_8_0_d.h3869 #define mmDP1_DP_DPHY_CNTL 0x1fd0 macro
H A Ddce_10_0_d.h4501 #define mmDP1_DP_DPHY_CNTL 0x4baf macro
H A Ddce_11_0_d.h4479 #define mmDP1_DP_DPHY_CNTL 0x4baf macro
H A Ddce_11_2_d.h5711 #define mmDP1_DP_DPHY_CNTL 0x4baf macro
H A Ddce_12_0_offset.h10510 #define mmDP1_DP_DPHY_CNTL … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h8679 #define mmDP1_DP_DPHY_CNTL … macro