Home
last modified time | relevance | path

Searched refs:mmHDMI_ACR_44_0 (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c1473 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1475 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
H A Ddce_v11_0.c1515 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1517 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3852 #define mmHDMI_ACR_44_0 0x1C39 macro
H A Ddce_8_0_d.h3199 #define mmHDMI_ACR_44_0 0x1c39 macro
H A Ddce_10_0_d.h3978 #define mmHDMI_ACR_44_0 0x4a30 macro
H A Ddce_11_0_d.h3847 #define mmHDMI_ACR_44_0 0x4a30 macro
H A Ddce_11_2_d.h5078 #define mmHDMI_ACR_44_0 0x4a30 macro