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Searched refs:mmHDMI_ACR_48_1 (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c1483 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1485 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
H A Ddce_v11_0.c1525 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1527 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3855 #define mmHDMI_ACR_48_1 0x1C3C macro
H A Ddce_8_0_d.h3223 #define mmHDMI_ACR_48_1 0x1c3c macro
H A Ddce_10_0_d.h4002 #define mmHDMI_ACR_48_1 0x4a33 macro
H A Ddce_11_0_d.h3877 #define mmHDMI_ACR_48_1 0x4a33 macro
H A Ddce_11_2_d.h5108 #define mmHDMI_ACR_48_1 0x4a33 macro