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Searched refs:mmLB_SYNC_RESET_SEL (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/display/dc/dce110/
H A Ddce110_compressor.c118 value = dm_read_reg(ctx, mmLB_SYNC_RESET_SEL); in reset_lb_on_vblank()
121 dm_write_reg(ctx, mmLB_SYNC_RESET_SEL, value); in reset_lb_on_vblank()
135 value = dm_read_reg(ctx, mmLB_SYNC_RESET_SEL); in reset_lb_on_vblank()
138 dm_write_reg(ctx, mmLB_SYNC_RESET_SEL, value); in reset_lb_on_vblank()
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3944 #define mmLB_SYNC_RESET_SEL 0x1ACA macro
H A Ddce_8_0_d.h4621 #define mmLB_SYNC_RESET_SEL 0x1acc macro
H A Ddce_10_0_d.h5302 #define mmLB_SYNC_RESET_SEL 0x1acc macro
H A Ddce_11_0_d.h5360 #define mmLB_SYNC_RESET_SEL 0x1acc macro
H A Ddce_11_2_d.h6617 #define mmLB_SYNC_RESET_SEL 0x1acc macro