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Searched refs:mmOUTPUT_CSC_CONTROL (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Ddce_v10_0.c2142 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_crtc_load_lut()
2145 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_crtc_load_lut()
H A Ddce_v11_0.c2176 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_crtc_load_lut()
2178 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_crtc_load_lut()
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3996 #define mmOUTPUT_CSC_CONTROL 0x1A3C macro
H A Ddce_8_0_d.h1948 #define mmOUTPUT_CSC_CONTROL 0x1a3c macro
H A Ddce_10_0_d.h2797 #define mmOUTPUT_CSC_CONTROL 0x1a3c macro
H A Ddce_11_0_d.h2551 #define mmOUTPUT_CSC_CONTROL 0x1a3c macro
H A Ddce_11_2_d.h3782 #define mmOUTPUT_CSC_CONTROL 0x1a3c macro