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Searched refs:mmSCL1_SCL_UPDATE (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h4161 #define mmSCL1_SCL_UPDATE 0x1E51 macro
H A Ddce_8_0_d.h4932 #define mmSCL1_SCL_UPDATE 0x1e51 macro
H A Ddce_10_0_d.h5648 #define mmSCL1_SCL_UPDATE 0x1d51 macro
H A Ddce_11_0_d.h5706 #define mmSCL1_SCL_UPDATE 0x1d51 macro
H A Ddce_11_2_d.h7033 #define mmSCL1_SCL_UPDATE 0x1d51 macro
H A Ddce_12_0_offset.h4784 #define mmSCL1_SCL_UPDATE … macro