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Searched refs:mmVGA_INTERRUPT_CONTROL (Results 1 – 7 of 7) sorted by relevance

/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h4385 #define mmVGA_INTERRUPT_CONTROL 0x00D1 macro
H A Ddce_8_0_d.h5152 #define mmVGA_INTERRUPT_CONTROL 0xd1 macro
H A Ddce_10_0_d.h6035 #define mmVGA_INTERRUPT_CONTROL 0xd1 macro
H A Ddce_11_0_d.h6112 #define mmVGA_INTERRUPT_CONTROL 0xd1 macro
H A Ddce_11_2_d.h7786 #define mmVGA_INTERRUPT_CONTROL 0xd1 macro
H A Ddce_12_0_offset.h580 #define mmVGA_INTERRUPT_CONTROL … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h414 #define mmVGA_INTERRUPT_CONTROL … macro