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Searched refs:mmVGA_RENDER_CONTROL (Results 1 – 13 of 13) sorted by relevance

/dragonfly/sys/dev/drm/amd/amdgpu/
H A Dcik.c903 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); in cik_read_disabled_bios()
917 WREG32(mmVGA_RENDER_CONTROL, in cik_read_disabled_bios()
929 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); in cik_read_disabled_bios()
H A Dvi.c387 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); in vi_read_disabled_bios()
401 WREG32(mmVGA_RENDER_CONTROL, in vi_read_disabled_bios()
413 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); in vi_read_disabled_bios()
H A Dgmc_v7_0.c281 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v7_0_mc_program()
283 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v7_0_mc_program()
H A Dgmc_v8_0.c472 tmp = RREG32(mmVGA_RENDER_CONTROL); in gmc_v8_0_mc_program()
474 WREG32(mmVGA_RENDER_CONTROL, tmp); in gmc_v8_0_mc_program()
H A Ddce_v10_0.c443 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v10_0_set_vga_render_state()
448 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v10_0_set_vga_render_state()
H A Ddce_v11_0.c459 tmp = RREG32(mmVGA_RENDER_CONTROL); in dce_v11_0_set_vga_render_state()
464 WREG32(mmVGA_RENDER_CONTROL, tmp); in dce_v11_0_set_vga_render_state()
/dragonfly/sys/dev/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h4393 #define mmVGA_RENDER_CONTROL 0x00C0 macro
H A Ddce_8_0_d.h5133 #define mmVGA_RENDER_CONTROL 0xc0 macro
H A Ddce_10_0_d.h6016 #define mmVGA_RENDER_CONTROL 0xc0 macro
H A Ddce_11_0_d.h6093 #define mmVGA_RENDER_CONTROL 0xc0 macro
H A Ddce_11_2_d.h7767 #define mmVGA_RENDER_CONTROL 0xc0 macro
H A Ddce_12_0_offset.h554 #define mmVGA_RENDER_CONTROL … macro
/dragonfly/sys/dev/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h388 #define mmVGA_RENDER_CONTROL … macro